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AD7228A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7228A
Beschreibung LC2MOS Octal 8-Bit DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
AD7228A Datasheet, Funktion
a
FEATURES
Eight 8-Bit DACs with Output Amplifiers
Operates with Single +5 V, +12 V or +15 V
or Dual Supplies
P Compatible (95 ns WR Pulse)
No User Trims Required
Skinny 24-Pin DlPs, SOIC, and 28-Terminal Surface
Mount Packages
LC2MOS
Octal 8-Bit DAC
AD7228A
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7228A contains eight 8-bit voltage-mode digital-to-
analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.
Separate on-chip latches are provided for each of the eight D/A
converters. Data is transferred into the data latches through a
common 8-bit TTL/CMOS (5 V) compatible input port. Ad-
dress inputs A0, A1 and A2 determine which latch is loaded
when WR goes low. The control logic is speed compatible with
most 8-bit microprocessors.
Specified performance is guaranteed for input reference voltages
from +2 to +10 V when using dual supplies. The part is also
specified for single supply +15 V operation using a reference of
+10 V and single supply +5 V operation using a reference of
+1.23 V. Each output buffer amplifier is capable of developing
+10 V across a 2 kload.
The AD7228A is fabricated on an all ion-implanted, high-
speed, Linear Compatible CMOS (LC2MOS) process which has
been specifically developed to integrate high-speed digital logic
circuits and precision analog circuits on the same chip.
PRODUCT HIGHLIGHTS
1. Eight DACs and Amplifiers in Small Package
The single-chip design of eight 8-bit DACs and amplifiers al-
lows a dramatic reduction in board space requirements and
offers increased reliability in systems using multiple convert-
ers. Its pinout is aimed at optimizing board layout with all
analog inputs and outputs at one side of the package and all
digital inputs at the other.
2. Single or Dual Supply Operation
The voltage-mode configuration of the DACs allows single
supply operation of the AD7228A. The part can also be oper-
ated with dual supplies giving enhanced performance for
some parameters.
3. Microprocessor Compatibility
The AD7228A has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered and speed compatible with most high per-
formance 8-bit microprocessors.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD7228A Datasheet, Funktion
AD7228A
Table II. Unipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1111
1000
1000
0111
0000
1111
0001
0000
1111
0001
+V
REF

255
256

+V
REF

129
256

+V
REF

128
256

=
+
V
REF
2
+V
REF

127
256

+V
REF

1
256

0000 0000
0V
Note: 1 LSB = (VREF)(2–8) = VREF

1
256

BIPOLAR OUTPUT OPERATION
Each of the DACs on the AD7228A can be individually config-
ured for bipolar output operation. This is possible using one ex-
ternal amplifier and two resistors per channel. Figure 8 shows a
circuit used to implement offset binary coding (bipolar opera-
tion) with DAC1 of the AD7228A. In this case
( ) ( )VOUT
=
1 +
R2
R1

D1 V REF

R2
R1

V REF
With R1 = R2
VOUT = (2D1 – 1) • (VREF)
where D1 is a fractional representation of the digital word in
latch 1 of the AD7228A. (0 D1 255/256)
Mismatch between R1 and R2 causes gain and offset errors, and
therefore, these resistors must match and track over temperature.
Once again, the AD7228A can be operated from single supply
or from dual supplies. Table III shows the digital code versus
output voltage relationship for the circuit of Figure 8 with
R1 = R2.
AC REFERENCE SIGNAL
In some applications it may be desirable to have an ac signal ap-
plied as the reference input to the AD7228A. The AD7228A
has multiplying capability within the upper (+10 V) and lower
(+2 V) limits of reference voltage when operated with dual sup-
plies. Therefore, ac signals need to be ac coupled and biased up
before being applied to the reference input. Figure 9 shows a
sine-wave signal applied to the reference input of the AD7228A.
For input frequencies up to 50 kHz, the output distortion typi-
cally remains less than 0.1%. The typical 3 dB bandwidth for
small signal inputs is 800 kHz.
Figure 9. Applying a AC Signal to the AD7228A
TIMING DESKEW
A common problem in ATE applications is the slowing or
“rounding-off” of signal edges by the time they reach the
pin-driver circuitry. This problem can easily be overcome by
“squaring-up” the edge at the pin-driver. However, since each
edge will not have been “rounded-off” by the same extent, this
“squaring-up” could lead to incorrect timing relationship be-
tween signals. This effect is shown in Figure 10a.
Figure 8. Bipolar Output Circuit
Table III. Bipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1111
1000
1111
0001
+V
REF

127
128

+V
REF

1
128

1000
0111
0000
0000
0000
1111
0001
0000
0V
V
REF

1
128

V
REF

127
128

V REF

128
128

=
V REF
Figure 10a. Time Skewing Due to Slowing of Edges
The circuit of Figure 10b shows how two DACs of the
AD7228A can help in overcoming this problem. The same two
signals are applied to this circuit as were applied in Figure 10b.
The output of each DAC is applied to one input of a high-speed
comparator, and the signals are applied to the other inputs.
Varying the output voltage of the DAC effectively varies the
trigger point at which the comparator flips. Thus the timing re-
lationship between the two signals can be programmably cor-
rected (or deskewed) by varying the code to the DAC of the
AD7228A. In a typical application, the code is loaded to the
–6– REV. A

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