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PDF AD7226 Data sheet ( Hoja de datos )

Número de pieza AD7226
Descripción LC2MOS Quad 8-Bit D/A Converter
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
FEATURES
Four 8-Bit DACs with Output Amplifiers
Skinny 20-Pin DIP, SOIC and 20-Terminal
Surface Mount Packages
Microprocessor Compatible
TTL/CMOS Compatible
No User Trims
Extended Temperature Range Operation
Single Supply Operation Possible
APPLICATIONS
Process Control
Automatic Test Equipment
Automatic Calibration of Large System Parameters,
e.g., Gain/Offset
LC2MOS
Quad 8-Bit D/A Converter
AD7226
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7226 contains four 8-bit voltage-output digital-to-
analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.
Separate on-chip latches are provided for each of the four D/A
converters. Data is transferred into one of these data latches
through a common 8-bit TTL/CMOS (5 V) compatible input
port. Control inputs A0 and A1 determine which DAC is loaded
when WR goes low. The control logic is speed-compatible with
most 8-bit microprocessors.
Each D/A converter includes an output buffer amplifier capable
of driving up to 5 mA of output current. The amplifiers’ offsets
are laser-trimmed during manufacture, thereby eliminating any
requirement for offset nulling.
Specified performance is guaranteed for input reference voltages
from +2 V to +12.5 V with dual supplies. The part is also speci-
fied for single supply operation at a reference of +10 V.
The AD7226 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC2MOS) process which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
PRODUCT HIGHLIGHTS
1. DAC-to-DAC Matching
Since all four DACs are fabricated on the same chip at the
same time, precise matching and tracking between the DACs
is inherent.
2. Single Supply Operation
The voltage mode configuration of the DACs allows the
AD7226 to be operated from a single power supply rail.
3. Microprocessor Compatibility
The AD7226 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered.
4. Small Size
Combining four DACs and four op amps plus interface logic
into a 20-pin DIP or SOIC or a 20-terminal surface mount
package allows a dramatic reduction in board space require-
ments and offers increased reliability in systems using mul-
tiple converters. Its pinout is aimed at optimizing board
layout with all the analog inputs and outputs at one end of the
package and all the digital inputs at the other.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

1 page




AD7226 pdf
CIRCUIT INFORMATION
D/A SECTION
The AD7226 contains four, identical, 8-bit, voltage mode
digital-to-analog converters. The output voltages from the con-
verters have the same polarity as the reference voltage allowing
single supply operation. A novel DAC switch pair arrangement
on the AD7226 allows a reference voltage range from +2 V to
+12.5 V.
Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high speed NMOS, single-pole, double-throw
switches. The simplified circuit diagram for one channel is
shown in Figure 1. Note that VREF (Pin 4) and AGND (Pin 5)
are common to all four DACs.
AD7226
Figure 2. Amplifier Output Stage
the current load ceases to act as a current sink and begins to act
as a resistive load of approximately 2 kto AGND. This occurs
as the NMOS transistors come out of saturation. This means
that, in single supply operation, the sink capability of the ampli-
fiers is reduced when the output voltage is at or near AGND. A
typical plot of the variation of current sink capability with out-
put voltage is shown in Figure 3.
Figure 1. D/A Simplified Circuit Diagram
The input impedance at the VREF pin of the AD7226 is the par-
allel combination of the four individual DAC reference input
impedances. It is code dependent and can vary from 2 kto in-
finity. The lowest input impedance (i.e., 2 k) occurs when all
four DACs are loaded with the digital code 01010101. There-
fore, it is important that the reference presents a low output im-
pedance under changing load conditions. The nodal capacitance
at the reference terminals is also code dependent and typically
varies from 100 pF to 250 pF.
Each VOUT pin can be considered as a digitally programmable
voltage source with an output voltage of:
VOUTX = DX VREF
where DX is fractional representation of the digital input code
and can vary from 0 to 255/256.
The source impedance is the output resistance of the buffer
amplifier.
Figure 3. Variation of ISINK with VOUT
OP AMP SECTION
Each voltage-mode D/A converter output is buffered by a unity
gain, noninverting CMOS amplifier. This buffer amplifier is
capable of developing +10 V across a 2 kload and can drive
capacitive loads of 3300 pF. The output stage of this amplifier
consists of a bipolar transistor from the VDD line and a current
load to the VSS, the negative supply for the output amplifiers.
This output stage is shown in Figure 2.
The NPN transistor supplies the required output current drive
(up to 5 mA). The current load consists of NMOS transistors
which normally act as a constant current sink of 400 µA to VSS,
giving each output a current sink capability of approximately
400 µA if required.
The AD7226 can be operated single or dual supply resulting
in different performance in some parameters from the output
amplifiers.
In single supply operation (VSS = 0 V = AGND), with the out-
put approaching AGND (i.e., digital code approaching all 0s)
If the full sink capability is required with output voltages at or
near AGND (=0 V), then VSS can be brought below 0 V by 5 V
and thereby maintain the 400 µA current sink as indicated in
Figure 3. Biasing VSS below 0 V also gives additional headroom
in the output amplifier which allows for better zero code error
performance on each output. Also improved is the slew-rate
and negative-going settling-time of the amplifiers (discussed
later).
Each amplifier offset is laser trimmed during manufacture to
eliminate any requirement for offset nulling.
DIGITAL SECTION
The digital inputs of the AD7226 are both TTL and CMOS
(5 V) compatible from VDD = +11.4 V to +16.5 V. All logic in-
puts are static protected MOS gates with typical input currents
of less than 1 nA. Internal input protection is achieved by an
on-chip distributed diode from DGND to each MOS gate. To
minimize power supply currents, it is recommended that the
digital input voltages be driven as close to the supply rails (VDD
and DGND) as practically possible.
REV. A
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AD7226 arduino
OFFSET ADJUST
Figure 21 shows how the AD7226 can be used to provide pro-
grammable input offset voltage adjustment for the AD544 op
amp. Each output of the AD7226 can be used to trim the input
offset voltage on one AD544. The 620 kresistor tied to +10 V
provides a fixed bias current to one offset node. For symmetrical
adjustment, this bias current should equal the current in the
other offset node with the half-full scale code (i.e., 10000000)
on the DAC. Changing the code on the DAC varies the bias
current and hence provides offset adjust for the AD544. For ex-
ample, the input offset voltage on the AD544J, which has a
maximum of ± 2 mV, can be programmably trimmed to ± 10 µV.
Microprocessor Interface
AD7226
Figure 21. Offset Adjust for AD544
Figure 22. AD7226 to 8085A Interface
Figure 24. AD7226 to 6502 Interface
Figure 23. AD7226 to 6809 Interface
Figure 25. AD7226 to Z-80 Interface
REV. A
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