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PDF AD7225 Data sheet ( Hoja de datos )
| Número de pieza | AD7225 | |
| Descripción | LC2MOS Quad 8-Bit DAC with Separate Reference Inputs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Four 8-Bit DACs with Output Amplifiers
Separate Reference Input for Each DAC
P Compatible with Double-Buffered Inputs
Simultaneous Update of All Four Outputs
Operates with Single or Dual Supplies
Extended Temperature Range Operation
No User Trims Required
Skinny 24-Pin DIP, SOIC and 28-Terminal Surface
Mount Packages
LC2MOS Quad 8-Bit DAC
with Separate Reference Inputs
AD7225
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7225 contains four 8-bit voltage output digital-to-
analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. Each D/A converter has a
separate reference input terminal. No external trims are re-
quired to achieve full specified performance for the part.
The double-buffered interface logic consists of two 8-bit regis-
ters per channel–an input register and a DAC register. Control
inputs A0 and A1 determine which input register is loaded when
WR goes low. Only the data held in the DAC registers deter-
mines the analog outputs of the converters. The double-
buffering allows simultaneous update of all four outputs under
control of LDAC. All logic inputs are TTL and CMOS (5 V)
level compatible and the control logic is speed compatible with
most 8-bit microprocessors.
Specified performance is guaranteed for input reference voltages
from +2 V to +12.5 V when using dual supplies. The part is also
specified for single supply operation using a reference of +10 V.
Each output buffer amplifier is capable of developing +10 V
across a 2 kΩ load.
The AD7225 is fabricated on an all ion-implanted high-speed
Linear Compatible CMOS (LC2MOS) process which has been
specifically developed to integrate high speed digital logic cir-
cuits and precision analog circuitry on the same chip.
PRODUCT HIGHLIGHTS
1. DACs and Amplifiers on CMOS Chip
The single-chip design of four 8-bit DACs and amplifiers al-
lows a dramatic reduction in board space requirements and
offers increased reliability in systems using multiple convert-
ers. Its pinout is aimed at optimizing board layout with all
analog inputs and outputs at one end of the package and all
digital inputs at the other.
2. Single or Dual Supply Operation
The voltage-mode configuration of the AD7225 allows single
supply operation. The part can also be operated with dual
supplies giving enhanced performance for some parameters.
3. Versatile Interface Logic
The AD7225 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. The double-buffered in-
terface allows simultaneous update of the four outputs.
4. Separate Reference Input for Each DAC
The AD7225 offers great flexibility in dealing with input sig-
nals with a separate reference input provided for each DAC
and each reference having variable input voltage capability.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
Typical Performance Characteristics–AD7225
TA = 25؇C, VDD = +15 V, VSS = –5 V unless otherwise noted.
Figure 1. Channel-to-Channel Matching
Figure 2. Relative Accuracy vs. VREF
Figure 3. Differential Nonlinearity vs. VREF
Figure 4. Power Supply Current vs. Temperature
Figure 5. Zero Code Error vs. Temperature
Figure 6. Broadband Noise
REV. B
–5–
5 Page 
MICROPROCESSOR INTERFACE
A15
A8
8085A/
8088
WR
ALE
AD7
AD0
ADDRESS BUS
ADDRESS
DECODE
LATCH
EN
A0
A1
LDAC
AD7225*
WR
DB7
DB0
ADDRESS DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 22. AD7225 to 8085A/8088 Interface,
Double-Buffered Mode
A15
A0
6809/
6502
R/W
E OR φ2
D7
D0
ADDRESS BUS
ADDRESS
DECODE
EN
A0
A1
LDAC
AD7225*
WR
DB7
DB0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 23. AD7225 to 6809/6502 Interface,
Single-Buffered Mode
A15
A8
Z-80
MREQ
WR
D7
D0
ADDRESS BUS
ADDRESS
DECODE
EN
A0
A1
LDAC
AD7225*
WR
DB7
DB0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 24. AD7225 to Z-80 Interface,
Double-Buffered Mode
AD7225
A23
A1
68008
AS
R/W
DTACK
D7
D0
ADDRESS BUS
ADDRESS
DECODE
EN
A0
A1
AD7225*
WR
LDAC
DB7
DB0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 25. AD7225 to 68008 Interface,
Single-Buffered Mode
VSS GENERATION
Operating the AD7225 from dual supplies results in enhanced
performance over single supply operation on a number of pa-
rameters as previously outlined. Some applications may require
this enhanced performance, but may only have a single power
supply rail available. The circuit of Figure 26 shows a method of
generating a negative voltage using one CD4049, operated from
a VDD of +15 V. Two inverters of the hex inverter chip are used
as an oscillator. The other four inverters are in parallel and used
as buffers for higher output current. The square-wave output is
level translated to a negative-going signal, then rectified and fil-
tered. The circuit configuration shown will provide an output
voltage of –5.1 V for current loadings in the range 0.5 mA to
9 mA. This will satisfy the AD7225 ISS requirement over the
commercial operating temperature range.
1/6 1/6
CD4049AE CD4049AE
510k
5.1k
0.02µF
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
47µF
+
510Ω
1N4001
1N4001
47µF
+
–VOUT
5V1
Figure 26. VSS Generation Circuit
REV. B
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD7225.PDF ] | |
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