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AD712 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD712
Beschreibung High Speed BiFET Dual Op Amp
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD712 Datasheet, Funktion
FEATURES
Enhanced replacement for LF412 and TL082
AC performance
Settles to ±0.01% in 1.0 μs
16 V/μs minimum slew rate (AD712J)
3 MHz minimum unity-gain bandwidth (AD712J)
DC performance
200 V/mV minimum open-loop gain (AD712K)
Surface mount available in tape and reel in
accordance with the EIA-481A standard
MIL-STD-883B parts available
Single version available: AD711
Quad version: AD713
Available in PDIP, SOIC_N, and CERDIP packages
GENERAL DESCRIPTION
The AD712 is a high speed, precision, monolithic operational
amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that
use older precision BiFETs and, in many cases, bipolar op amps.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16 V/μs
and a settling time of 1 μs to ±0.01%, the AD712 is ideal as a
buffer for 12-bit digital-to-analog converters (DACs) and analog-
to-digital converters (ADCs) and as a high speed integrator.
The settling time is unmatched by any similar IC amplifier.
The combination of excellent noise performance and low input
current also make the AD712 useful for photo diode preamps.
Common-mode rejection of 88 dB and open-loop gain of
400 V/mV ensure 12-bit performance even in high speed
unity-gain buffer circuits.
The AD712 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD712J and
AD712K are rated over the commercial temperature range of
0°C to 70°C. The AD712A is rated over the industrial tempera-
ture range of −40°C to +85°C. The AD712S is rated over the
military temperature range of −55°C to +125°C and is available
processed to MIL-STD-883B, Rev. C.
Precision, Low Cost,
High Speed BiFET Dual Op Amp
AD712
CONNECTION DIAGRAM
AMPLIFIER NO. 1
AMPLIFIER NO. 2
OUTPUT 1
8 V+
INVERTING
INPUT
NONINVERTING
INPUT
2
3
V– 4
AD712
7 OUTPUT
6
INVERTING
INPUT
5
NONINVERTING
INPUT
Figure 1. 8-Lead PDIP (N-Suffix),
SOIC_N (R-Suffix), and CERDIP (Q-Suffix)
Extended reliability PLUS screening is available, specified
over the commercial and industrial temperature ranges. PLUS
screening includes 168-hour burn-in, in addition to other
environmental and physical tests.
The AD712 is available in 8-lead PDIP, SOIC_N, and CERDIP
packages.
PRODUCT HIGHLIGHTS
1. The AD712 offers excellent overall performance at very
competitive prices.
2. The Analog Devices, Inc., advanced processing technology
and 100% testing guarantee a low input offset voltage (3
mV maximum, J grade). Input offset voltage is specified in
the warmed-up condition.
3. Together with precision dc performance, the AD712 offers
excellent dynamic response. It settles to ±0.01% in 1 μs and
has a minimum slew rate of 16 V/μs. Thus, this device is
ideal for applications such as DAC and ADC buffers that
require a combination of superior ac and dc performance.
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1986–2010 Analog Devices, Inc. All rights reserved.






AD712 Datasheet, Funktion
AD712
TYPICAL PERFORMANCE CHARACTERISTICS
20
15
10
RL = 2k
25°C
5
0
0 5 10 15
SUPPLY VOLTAGE ± V
Figure 2. Input Voltage Swing vs. Supply Voltage
20
20
15
+VOUT
–VOUT
10
RL = 2k
25°C
5
0
0 5 10 15
SUPPLY VOLTAGE ± V
Figure 3. Output Voltage Swing vs. Supply Voltage
20
30
25
20
±15V SUPPLIES
15
10
5
0
10 100
1k
LOAD RESISTANCE ()
10k
Figure 4. Output Voltage Swing vs. Load Resistance
6
5
4
3
2
0 5 10 15
SUPPLY VOLTAGE ± V
Figure 5. Quiescent Current vs. Supply Voltage
20
106
107
108
109
1010
1011
1012
–60
–40 –20
0 20 40 60 80
TEMPERATURE (°C)
100 120
Figure 6. Input Bias Current vs. Temperature
140
100
10
1.0
0.1
0.01
1k
10k 100k 1M
FREQUENCY (Hz)
Figure 7. Output Impedance vs. Frequency
10M
Rev. H | Page 6 of 20

6 Page









AD712 pdf, datenblatt
AD712
OP AMP SETTLING TIME—A MATHEMATICAL
MODEL
The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful trade-off
was made: the gain bandwidth product (4 MHz) and slew rate
(20 V/μs) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction
in phase margin (and therefore, stability). Thus designed, the
AD712 settles to ±0.01%, with a 10 V output step, in under 1 μs,
while retaining the ability to drive a 250 pF load capacitance
when operating as a unity-gain follower.
If an op amp is modeled as an ideal integrator with a unity-gain
crossover frequency of ωO/2π, then Equation 1 accurately
describes the small signal behavior of the circuit of Figure 32,
consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com-
pletely describe the output of the system if not for the finite slew
rate and other nonlinear effects of the op amp.
VO =
R
I IN
R(CX
ωO
)
s2
+
⎜⎜⎝⎛
GN
ωO
+ RC f
⎟⎟⎠⎞
s +1
(1)
Where
ωO = unity-gain frequency of the op amp.
2π
GN
=
noise
gain
of
circuit
⎜⎜⎝⎛1 +
R
RO
⎟⎟⎠⎞
.
This equation can then be solved for Cf
( )CX
= 2 GN
RωO
+2
RCXωO + 1 GN
RωO
(2)
In these equations, Capacitance CX is the total capacitance
appearing at the inverting terminal of the op amp. When
modeling a DAC buffer application, the Norton equivalent
circuit shown in Figure 32 can be used directly; Capacitance CX
is the total capacitance of the output of the DAC plus the input
capacitance of the op amp (because the two are in parallel).
IO RO
+ 1/2
AD712
CF
R
CX
VOUT
RL CL
Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer
When RO and IO are replaced with their Thevenin VIN and RIN
equivalents, the general-purpose inverting amplifier shown in
Figure 33 is created. Note that when using this general model,
Capacitance CX is either the input capacitance of the op amp, if
a simple inverting op amp is being simulated, or the combined
capacitance of the DAC output and the op amp input if the
DAC buffer is being modeled.
+ 1/2
AD712
CF
RIN R
VIN CX
VOUT
RL CL
Figure 33. Simplified Model of the AD712 Used as an Inverter
In either case, Capacitance CX causes the system to go from a
one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Because the value of CX can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor
(CF) to cancel the input pole and optimize amplifier response.
Figure 34 is a graphical solution of Equation 2 for the AD712
with R = 4 kΩ.
60
50
40 GN = 4.0
30
GN = 3.0
20
10
GN = 2.0
GN = 1.5
GN = 1.0
0
0 10 20 30 40 50
CF
Figure 34. Value of Capacitor CF vs. Value of CX
60
Rev. H | Page 12 of 20

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