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PDF AD7118 Data sheet ( Hoja de datos )
| Número de pieza | AD7118 | |
| Descripción | LOGDAC CMOS Logarithmic D/A Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
LOGDAC
CMOS Logarithmic D/A Converter
AD7118*
FEATURES
Dynamic Range 85.5 dB
Resolution 1.5 dB
Full ؎25 V Input Range Multiplying DAC
Full Military Temperature Range –55؇C to +125؇C
Low Distortion
Low Power Consumption
Latch Proof Operation (Schottky Diodes Not Required)
Single 5 V to 15 V Supply
APPLICATIONS
Digitally Controlled AGC Systems
Audio Attenuators
Wide Dynamic Range A/D Converters
Sonar Systems
Function Generators
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
GENERAL DESCRIPTION
The LOGDAC® AD7118 is a CMOS multiplying D/A con-
verter which attenuates an analog input signal over the range
0 to –85.5 dB in 1.5 dB steps. The analog output is determined
by a six-bit attenuation code applied to the digital inputs.
Operating frequency range of the device is from dc to several
hundred kHz.
The device is manufactured using an advanced monolithic
silicon gate thin-film on CMOS process and is packaged in a
14-pin dual-in-line package.
ORDERING INFORMATION
Model
Temperature
Range
Specified
Accuracy
Range
Package
Option1
AD7118KN
AD7118LN
AD7118BQ
AD7118CQ
AD7118TQ2
AD7118UQ2
0°C to +70°C
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
0 to 42 dB
0 to 48 dB
0 to 42 dB
0 to 48 dB
0 to 42 dB
0 to 48 dB
N-16
N-16
Q-16
Q-16
Q-16
Q-16
NOTES
1N = Plastic DIP; Q = Cerdip.
2To order MIL-STD-883, Class B processed parts, add /883B to part number.
*Protected by U.S. Patent No. 4521,764.
LOGDAC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
Applications Information–AD7118
DYNAMIC PERFORMANCE
The dynamic performance of the AD7118 will depend upon the
gain and phase characteristics of the output amplifier, together
with the optimum choice of PC board layout and decoupling
components. Figure 4 shows a printed circuit layout which
minimizes feedthrough from VIN to the output in multiplying
applications. Circuit layout is most important if the optimum
performance of the AD7118 is to be achieved. Most application
problems stem from either poor layout, grounding errors, or in-
appropriate choice of amplifier.
coupling across the parasitic capacitance. It should be noted
that the accuracy of the AD7118 improves as VDD is increased
(see Figure 8) but the device maintains monotonic behavior to
at least –66 dB in the range 5 ≤ VDD ≤ 15 volts.
For operation beyond 250 kHz, capacitor C1 may be reduced in
value. This gives an increase in bandwidth at the expense of a
poorer transient response as shown in Figures 6 and 11. In cir-
cuits where C1 is not included the high frequency roll-off point
is primarily determined by the characteristics of the output am-
plifier and not the AD7118.
Feedthrough and absolute accuracy for attenuation levels be-
yond 42 dB are sensitive to output leakage current effects. For
this reason it is recommended that the operating temperature of
the AD7118 be kept as close to 25°C as is practically possible,
particularly where the device’s performance at high attenuation
levels is important. A typical plot of leakage current vs. tempera-
ture is shown in Figure 10.
Figure 4. Suggested Layout for AD7118 and Op Amp
It is recommended that when using the AD7118 with a high
speed amplifier, a capacitor C1 be connected in the feedback
path as shown in Figure 1. This capacitor, which should be
between 30 pF and 50 pF, compensates for the phase lag intro-
duced by the output capacitance of the D/A converter. Figures 5
and 6 show the performance of the AD7118 using the AD517, a
fully compensated high gain superbeta amplifier, and the
AD544, a fast FET input amplifier. The performance without
C1 is shown in the middle trace and the response with C1 in
circuit is shown in the bottom trace.
Some solder fluxes and cleaning materials can form slightly con-
ductive films which cause leakage effects between analog input
and output. The user is cautioned to ensure that the manufac-
turing process for circuits using the AD7118 does not allow
such films to form. Otherwise the feedthrough, accuracy and
maximum usable range will be affected.
STATIC ACCURACY PERFORMANCE
The D/A converter section of the AD7118 consists of a 17-bit
R-2R type converter. To obtain optimum static performance at
this level of resolution it is necessary to pay great attention to
amplifier selection, circuit grounding, etc.
Amplifier input bias current results in a dc offset at the output
of the amplifier due to the current flowing through the feedback
resistor RFB. It is recommended that an amplifier with an input
bias current of less than 10 nA be used (e.g., AD517 or AD544)
to minimize this offset.
Figure 5. Response of AD7118 with AD517L
Another error arises from the output amplifier’s input offset
voltage. The amplifier is operated with a fixed feedback resis-
tance, but the equivalent source impedance (the AD7118 out-
put impedance) varies as a function of attenuation level. This
has the effect of varying the “noise” gain of the amplifier, thus
creating a varying error due to amplifier offset voltage. To
achieve an output offset error less than one half the smallest step
size, it is recommended that an amplifier with less than 50 µV of
input offset be used (such as the AD517 or AD OP07).
If dc accuracy is not critical in the application, it should be
noted that amplifiers with offset voltage up to approximately 2
millivolts can be used. Amplifiers with higher offset voltage may
cause audible “thumps” due to dc output changes.
Figure 6. Response of AD7118 with AD544S
In conventional CMOS D/A converter design parasitic
capacitance in the N-channel D/A converter switches can give
rise to glitches on the D/A converter output. These glitches re-
sult from digital feedthrough. The AD7118 has been designed
to minimize these glitches as much as possible. It is recom-
mended that for minimum glitch energy the AD7118 be oper-
ated with VDD = 5 V. This will reduce the available energy for
The AD7118 accuracy is specified and tested using only the
internal feedback resistor. It is not recommended that “gain”
trim resistors be used with the AD7118 because the internal
logic of the circuit executes a proprietary algorithm which ap-
proximates a logarithmic curve with a binary D/A converter: as a
result no single point on the attenuator transfer function can be
guaranteed to lie exactly on the theoretical curve. Any “gain-
error” (i.e., mismatch of RFB to the R-2R ladder) that may exist
in the AD7118 D/A converter circuit results in a constant
attenuation error over the whole range. Since the gain error of
CMOS multiplying D/A converters is normally less than 1%,
the accuracy error contribution due to “gain error” effects is
normally less than 0.09 dB.
REV. A
–5–
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