Datenblatt-pdf.com


AD7112 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7112
Beschreibung LC2MOS LOGDAC Dual Logarithmic D/A Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
AD7112 Datasheet, Funktion
a
FEATURES
Dynamic Range: 88.5 dB
Resolution: 0.375 dB
On-Chip Data Latches for Both DACs
Four-Quadrant Multiplication
+5 V Operation
Pin Compatible with AD7528
Low Power
APPLICATIONS
Audio Attenuators
Sonar Systems
Function Generators
LC2MOS LOGDAC
Dual Logarithmic D/A Converter
AD7112*
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN A
AD7112
17-BIT DAC A
RFB A
OUT A
DB0
DB7
8-BIT
BUFFER
CONTROL
LOGIC
17-BIT LATCH
DECODE LOGIC
17-BIT1L7ATCH
17-BIT DAC B
RFB B
OUT B
GENERAL DESCRIPTION
The LOGDAC® AD7112 is a monolithic dual multiplying D/A
converter featuring wide dynamic range and excellent DAC-to-
DAC matching. Both DACs can attenuate an analog input sig-
nal over the range 0 dB to 88.5 dB in 0.375 dB steps. It is
available in skinny 0.3" wide 20-pin DIPs and in 20-terminal
surface mount packages.
The degree of attenuation in either channel is determined by the
8-bit word applied to the onboard decode logic. This 8-bit word
is decoded into a 17-bit word which is then loaded into one of
the 17-bit data latches, determined by DACA/DACB. The fine
step resolution over the entire dynamic range is due to the use of
these 17-bit DACs.
The AD7112 is easily interfaced to a standard 8-bit MPU bus
via an 8-bit data port and standard microprocessor control lines.
It should be noted that the AD7112 is exactly pin-compatible
with the AD7528, an industry standard dual 8-bit multiplying
DAC. This allows an easy upgrading of existing AD7528 de-
signs which would benefit both from the wider dynamic range
and the finer step resolution offered by the AD7112.
The AD7112 is fabricated in Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
*Protected by U.S. Patent No. 4521764.
LOGDAC is a registered trademark of Analog Devices, Inc.
DAC A/ CS WR VIN B
DAC B
DGND
AGND
PRODUCT HIGHLIGHTS
1. DAC-to-DAC Matching: Since both of the AD7112 DACs
are fabricated at the same time on the same chip, precise
matching and tracking between the two DACs is inherent.
2. Small Package: The AD7112 is available in a 20-pin DIP
and a 20-terminal SOIC package.
3. Fast Microprocessor Interface: The AD7112 has bus inter-
face timing compatible with all modern microprocessors.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD7112 Datasheet, Funktion
AD7112
INTERFACE LOGIC INFORMATION
DAC Selection
Both DAC latches share a common 8-bit port. The control in-
put DAC A/DAC B selects which DAC can accept data from
the input port.
Mode Selection
Inputs CS and WR control the operating mode of the selected
DAC. See the Mode Selection Table below.
Write Mode
When CS and WR are both low the DAC is in the write mode.
The input data latches of the selected DAC are transparent and
its analog output responds to activity on DB0–DB7.
Hold Mode
The selected DAC latch retains the data which was present on
DB0–DB7 just prior to CS and WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection Table
DACA/
DAC B
CS
WR DAC A
L L L WRITE
H L L HOLD
X H X HOLD
X X H HOLD
L = Low State, VIL; H = High State, VIH; X = Don’t Care.
DAC B
HOLD
WRITE
HOLD
HOLD
CS
DAC A/DAC B
tCS
tCH
tAH
tAS
WR
tWR
DB0–DB7
tDS
VIH
VIL
tDH
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM
10% TO 90% OF VDD. tR = tF = 20ns.
2. CONTROL TIMING MEASUREMENT REFERENCE LEVEL = (VIH + VIL) / 2
Figure 3. Write Cycle Timing Diagram
DYNAMIC PERFORMANCE
The dynamic performance of the AD7112 will depend on the
gain and phase characteristics of the output amplifier, together
with the optimum choice of PC board layout and decoupling
components. Circuit layout is most important if the optimum
performance of the AD7112 is to be achieved. Most application
problems stem from either poor layout, grounding errors, or in-
appropriate choice of amplifier. Ensure that the layout of the
printed circuit board has the digital and analog lines separated
as much as possible. Take care not to run any digital track
alongside an analog signal track. Establish a single point analog
ground (star ground) separate from the logic system ground.
Place this ground as close as possible to the AD7112. Connect
all analog grounds to this star ground, and also connect the
AD7112 DGND to this ground. Do not connect any other digi-
tal grounds to this analog ground point. Low impedance analog
and digital power supply common returns are essential for low
noise and high performance of these converters, therefore the
foil width of these tracks should be as wide as possible. The use
of ground planes is recommended as this minimizes impedance
paths and also guards the analog circuitry from digital noise.
It is recommended that when using the AD7112 with a high
speed amplifier, a capacitor (C1) be connected in the feedback
path as shown in Figure 2. This capacitor which should be be-
tween 5 pF and 15 pF, compensates for the phase lag intro-
duced by the output capacitance of the D/A converter. Figures
4 and 5 show the performance of the AD7112 using the
AD712, a high speed, low cost BiFET amplifier, and the
OP275, a dual bipolar/JFET amplifier suitable for audio appli-
cations. The performance with and without the compensation
capacitor is shown in both cases. For operation beyond
250 kHz, capacitor C1 may be reduced in value. This gives an
increase in bandwidth at the expense of a poorer transient re-
sponse as shown in Figure 7. In circuits where C1 is not in-
cluded, the high frequency roll-off point is primarily determined
by the characteristics of the output amplifier and not the AD7112.
Feedthrough and accuracy are sensitive to output leakage cur-
rents effects. For this reason it is recommended that the operat-
ing temperature of the AD7112 be kept as close to +25°C as is
practically possible, particularly where the devices performance
at high attenuation levels is important. A typical plot of leakage
current vs. temperature is shown in Figure 11.
Some solder fluxes and cleaning materials can form slightly
conductive films which cause leakage effects between analog in-
put and output. The user is cautioned to ensure that the manu-
facturing process for circuits using the AD7112 does not allow
such films to form. Otherwise the feedthrough, accuracy and
maximum usable range will be affected.
STATIC ACCURACY PERFORMANCE
The D/A converter section of the AD7112 consists of a 17-bit
R–2R type converter. To obtain optimum static performance at
this level of resolution it is necessary to pay great attention to
amplifier selection, circuit grounding, etc.
Amplifier input bias current results in a dc offset at the output
of the amplifier due to current flowing in the feedback resistor
RFB. It is recommended that amplifiers with input bias currents
of less than 10 nA be used (e.g., AD712) to minimize this offset.
–6– REV. 0

6 Page









AD7112 pdf, datenblatt
AD7112
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Plastic DIP (N-20)
PIN 1
20
1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
1.060 (26.90)
0.925 (23.50)
0.100 (2.54)
BSC
11
0.280 (7.11)
0.240 (6.10)
10
0.060 (1.52)
0.015 (0.38)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.045 (1.15) PLANE
20-Pin SOIC (R-20)
20
PIN 1
1
0.5118 (13.00)
0.4961 (12.60)
11
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
10
0.0500 (1.27)
BSC
0.1043 (2.65)
0.0926 (2.35)
0.0291
0.0098
(0.74)
(0.25)
X
45°
0°- 8°
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
–12–
REV. 0

12 Page





SeitenGesamt 12 Seiten
PDF Download[ AD7112 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD711BiFET Op AmpAnalog Devices
Analog Devices
AD7110Digitally Controlled Audio AttenuatorAnalog Devices
Analog Devices
AD7111LC2MOS LOGDAC Logarithmic D/A ConverterAnalog Devices
Analog Devices
AD7111ALC2MOS LOGDAC Logarithmic D/A ConverterAnalog Devices
Analog Devices
AD7112LC2MOS LOGDAC Dual Logarithmic D/A ConverterAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche