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AD7013 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7013
Beschreibung CMOS TIA IS-54 Baseband Receive Port
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD7013 Datasheet, Funktion
a
CMOS
TIA IS-54 Baseband Receive Port
AD7013
FEATURES
Single +5 V Supply
Receive Channel
Differential or Single-Ended Analog Inputs
Auxiliary Set of Analog I & Q Inputs
Two Sigma-Delta A/D Converters
Choice of Two Digital FIR Filters
Root-Raised-Cosine Rx Filters, α = 0.35
Brick Wall FIR Rx Filters
On-Chip or User Rx Offset Calibration
ADC Sampling Vernier
Three Auxiliary DACs
On-Chip Voltage Reference
Low Active Power Dissipation, Typical 45 mW
Low Sleep Mode Power Dissipation, <50 µW
28-Pin SSOP
APPLICATIONS
American TIA Digital Cellular Telephony
American Analog Cellular Telephony
Digital Baseband Receivers
GENERAL DESCRIPTION
The AD7013 is a complete low power, CMOS, TIA IS-54 base-
band receive port with single +5 V power supply. The part is
designed to perform the baseband conversion of I and Q
waveforms in accordance with the American (TIA IS-54)
Digital Cellular Telephone system.
The receive path consists of two high performance sigma-delta
ADCs, each followed by a FIR digital filter. A primary and
auxiliary set of IQ differential analog inputs are provided,
where either can be selected as inputs to the sigma-delta
ADCs. Also, a choice of two frequency responses are available
for the receive FIR filters; a Root-Raised-Cosine filter for
digital mode or a brick wall response for analog mode.
Differential analog inputs are provided for both I and Q
channels. On-chip calibration logic is also provided to remove
either on-chip offsets or remove system offsets. A 16-bit serial
interface is provided, interfacing easily to most DSPs. The
receive path also provides a means to vary the sampling
instant, giving a resolution to 1/32 of a symbol interval.
The auxiliary section provides two 8-bit DACs and one 10-bit
DAC for functions such as automatic gain control (AGC),
automatic frequency control (AFC) and power amplifier
control.
As it is a necessity for all digital mobile systems to use the
lowest possible power, the device has receive and auxiliary
power down options. The AD7013 is housed in a space
efficient 28-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
DxCLK
DATA IN
FRAME IN
MODE1
FRAME OUT
Rx CLK
Rx DATA
Rx FRAME
MCLK
DGND VDD
AUX DAC1 AUX DAC2 AUX DAC3
FS ADJUST VAA AGND
SERIAL
INTERFACE
RECEIVE
CHANNEL
SERIAL
INTERFACE
10-BIT
AUX DAC
8-BIT
AUX DAC
8-BIT
AUX DAC
FULL-SCALE
ADJUST
LATCH
LATCH
OFFSET
ADJUST
ANALOG MODE
FIR DIGITAL FILTER
ROOT RAISED COSINE
FIR DIGITAL FILTER
LATCH
1.23V
REFERENCE
AD7013
∆Σ
MODULATOR
SWITCHED
CAP FILTER
MUX
OFFSET
ADJUST
ANALOG MODE
FIR DIGITAL FILTER
ROOT RAISED COSINE
FIR DIGITAL FILTER
∆Σ
MODULATOR
SWITCHED
CAP FILTER
MUX
AGND
AGND
BYPASS
IRx
IRx
AUX IRx
AUX IRx
QRx
QRx
AUX QRx
AUX QRx
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD7013 Datasheet, Funktion
AD7013
CONTROL SERIAL INTERFACE TIMING1
(VAA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND =0 V,
fMCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Limit at
TA = –40°C to +85°C
160
65
65
20
60
2t1
t1–20
t1–20
25
10
16t5
25
10
0
25
25
25
Units
ns min
ns min
ns min
ns min
ns max
ns
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
Description
MCLK Cycle Time
MCLK High Time
MCLK Low Time
MCLK Rising Edge to DxCLK Rising Edge Propagation Delay
DxCLK Cycle Time
DxCLK Minimum High Time
DxCLK Minimum Low Time
DxCLK Rising Edge to FRAME IN Setup Time
DxCLK Rising Edge to FRAME IN Hold Time
FRAME IN Cycle Time
DxCLK Rising Edge to DATA IN Setup Time
DxCLK Rising Edge to DATA IN Hold Time
FRAME IN Rising Edge to FRAME OUT Rising Edge Propagation Delay
MODE1 Low to FRAME OUT 3-STATE
MODE1 High to FRAME OUT Active
NOTE
1t14 is derived from the measured time taken by the FRAME OUT pin to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the Timing Characteristics is the
1.6mA IOL
MxCLK (I)
DxCLK (O)
t4
t8
FRAME IN (I)
DATA IN (I)
t13
FRAME OUT (O)
TO OUTPUT PIN
CL
50pF
200µA IOH
+2.1V
Figure 1. Load Circuit for Digital Outputs
t1 t2
t3
t5 t6
t9 t7
t10
t12
t11
DB9 DB8
DB1
DATA
DB0
A3 A0 S1 S0
ADDRESS
t14
3 – STATE
IGNORED
t15
MODE1 (I)
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT, MODE1 = LOGIC HIGH
Figure 2. 16-Bit Serial Interface for Writing to the AD7013 Internal Registers
–6– REV. A

6 Page









AD7013 pdf, datenblatt
AD7013
VBIAS + 0.65
VBIAS
IRx
QUANTIZATION NOISE
BAND OF
INTEREST
aa.
fs/2
388.8kHz
VBIAS – 0.65
IRx
10 … 00
00 … 00
ADC CODE
01 … 11
Figure 11. ADC Transfer Function for Differential
Operation
VBIAS + 1.3
NOISE SHAPING
BAND OF
INTEREST
bb.
fs/2
388.8kHzMHz
ROOT RAISED COSINE FIR FILTER
VBIAS
IRx
VBIAS – 1.3
IRx
BAND OF
INTEREST
c
fs/2
388.8kHz
c.
Figure 13. a. Effect of High Oversampling Ratio.
b. Use of Noise Shaping to Further Improve SNR.
c. Use of Digital Filtering to Remove the Out of Band
Quantization Noise
10 … 00
00 … 00
ADC CODE
01 … 11
Figure 12. ADC Transfer Function for Single-Ended
Operation
SIGMA-DELTA ADC
The AD7013 receive channels employ a sigma-delta conversion
technique, which provides a high resolution 15-bit output for both I
and Q channels with system filtering being implemented on-chip.
The output of the switched-capacitor filter is continuously sampled
at MCLK/8, by a charge-balanced modulator, and is converted
into a digital pulse train whose duty cycle contains the digital
information. Due to the high oversampling rate which spreads the
quantization noise from 0 to fS/2, the noise energy which is
contained in the band of interest is reduced (Figure 13a). To
reduce the quantization noise still further, a high order modulator is
employed to shape the noise spectrum, so that most of the noise
energy is shifted out of the band of interest (Figure 13b).
The digital filter that follows the modulator removes the large out
of band quantization noise (Figure 13c), while converting the
digital pulse train into parallel 15-bit wide binary data. The 15-bit
I and Q data plus an I/Q flag bit is made available, via a serial
interface, as a 16-bit word, MSB first.
Digital Filter
The digital filters used in the AD7013 receive section carry out two
important functions. First, they remove the out of band quantiza-
tion noise which is shaped by the analog modulator. Second, they
are also designed to perform system level filtering, providing the
Root-Raised Cosine filter as required for TIA IS-54.
Since digital filtering occurs after the A/D conversion process, it can
remove noise injected during the conversion process. Analog
filtering cannot do this. Also, the digital filter combines low
passband ripple with a steep roll off, while also maintaining a linear
phase response. This is very difficult to achieve with analog filters.
Filter Characteristics
The digital filter is a 256-tap FIR filter, clocked at 1/8 the master
clock frequency. A choice of two frequency responses are available:
a Root-Raised Cosine response (CR11 = 0) and a brick wall
response at 11.4 kHz (CR11 = 1) for analog mode. Figure 16 and
Figure 17 illustrate the respective frequency responses for both
digital mode and analog mode while Figure 18 compares the low
frequency response of the digital filters.
Due to the low-pass nature of the receive filters there is a settling
time associated with step input functions. Output data will not be
meaningful until all the digital filter taps have been loaded with
data samples taken after the step change. Hence, the AD7013
digital filters have a settling time of 256 × 8t1 (i.e., 329.2 µs when
MCLK = 6.2208 MHz and 400 µs when MCLK = 5.12 MHz).
–12–
REV. A

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