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AD7002 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7002
Beschreibung LC2MOS GSM Baseband I/O Port
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD7002 Datasheet, Funktion
a
FEATURES
Single +5 V Supply
Transmit Channel
On-Chip GMSK Modulator
Two 10-Bit D/A Converters
Analog Reconstruction Filters
Power-Down Mode
Receive Channel
Two Sigma-Delta A/D Converters
FIR Digital Filters
On-Chip Offset Calibration
Power-Down Mode
3 Auxiliary D/A Converters
Power-Down Modes
On-Chip Voltage Reference
Low Power
44-Lead PQFP
APPLICATIONS
GSM
PCN
LC2MOS
GSM Baseband I/O Port
AD7002
GENERAL DESCRIPTION
The AD7002 is a complete low power, two-channel, input/
output port with signal conditioning. The device is used as a
baseband digitization subsystem, performing signal conversion
between the DSP and the IF/RF sections in the Pan-European
telephone system (GSM).
The transmit path consists of an onboard digital modulator,
containing all the code necessary for performing Gaussian Mini-
mum Shift Keying (GMSK), two high accuracy, fast DACs with
output reconstruction filters. The receive path is composed of
two high performance sigma-delta ADCs with digital filtering. A
common bandgap reference feeds the ADCs and signal DACs.
Three control DACs (AUX DAC1 to AUX DAC3) are in-
cluded for such functions as AFC, AGC and carrier signal shap-
ing. In addition, AUX FLAG may be used for routing digital
control information through the device to the IF/RF sections.
As it is a necessity for all GSM mobile systems to use the lowest
power possible, the device has power-down or sleep options for
all sections (transmit, receive and auxiliary).
The AD7002 is housed in 44-lead PQFP (Plastic Quad Flatpack).
Tx SLEEP
Tx DATA
Tx CLK
THREE-STATE
ENABLE
Rx CLK
Rx DATA (I DATA)
Rx SYNC
I/Q (Q DATA)
RATE
MODE
AUX DATA
AUX CLK
AUX LATCH
Rx SLEEP1
Rx SLEEP2
FUNCTIONAL BLOCK DIAGRAM
DVDD DGND
AVDD AGND
GMSK PULSE
SHAPING ROM
10-BIT DAC
4TH ORDER BESSEL
LOW-PASS FILTER
AD7002
10-BIT DAC
2.5V
REFERENCE
4TH ORDER BESSEL
LOW-PASS FILTER
REFERENCE
OUTPUT BUFFER
RECEIVE
CHANNEL
SERIAL
INTERFACE
I CHANNEL
DIGITAL FIR FILTER
OFFSET REGISTER
OFFSET REGISTER
Q CHANNEL
DIGITAL FIR FILTER
Σ−∆ MODULATOR
SWITCH-CAP
FILTER
Σ−∆ MODULATOR
SWITCH-CAP
FILTER
I Tx
Q Tx
REF OUT
I Rx
Q Rx
16-BIT SHIFT REGISTER
9-BIT DAC 10-BIT DAC 8-BIT DAC
AUX
DAC 1
AUX
DAC 2
AUX
AUX
DAC 3 FLAG
CAL CLK2
CLK1 MZERO
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997






AD7002 Datasheet, Funktion
AD7002
INPUT CLOCK TIMING1
(AVDD = +5 V ؎ 10%; DVDD = +5 V ؎ 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted)
Parameter
Limit at
TA = –40؇C to +85؇C
Units
Description
t1 76
t2 30
t3 30
ns min
ns min
ns min
CLK1, CLK2, AUX CLK Cycle Time
CLK1, CLK2, AUX CLK High Time
CLK1, CLK2, AUX CLK Low Time
TRANSMIT SECTION TIMING (AVDD = +5 V ؎ 10%; DVDD = +5 V ؎ 10%; AGND = DGND = 0 V, fCLK1 = fCLK2 = 13 MHz;
TA = TMIN to TMAX, unless otherwise noted)
Parameter
Limit at
TA = –40؇C to +85؇C
Units
Description
t4 10
ns min
Tx SLEEP Hold Time
t5 20
ns min
Tx SLEEP Setup Time
t6 24 t1
ns min
Tx CLK Active After CLK1 Rising Edge Following
24 t1 + 80
ns max
Tx SLEEP Low
t7 48 t1
ns Tx CLK Cycle Time
t8 24 t1
ns Tx CLK High Time
t9 24 t1
ns Tx CLK Low Time
t10 0
ns min
Propagation Delay from CLK1 to Tx CLK
100 ns max
30 ns max
t11 30
t12 10
t13 0
23 t1
t14 10
t15 10
ns max
ns min
ns min
ns max
ns typ
ns typ
Data Setup Time
Data Hold Time
Tx CLK to Tx SLEEP Asserted for Last Tx CLK Cycle2
Digital Output Rise Time3
Digital Output Fall Time3
AUXILIARY DAC TIMING (AVDD = +5 V ؎ 10%; DVDD = +5 V ؎ 10%; AGND = DGND = 0 V, fAUX CLK = 13 MHz; TA = TMIN to TMAX,
unless otherwise noted)
Parameter
Limit at
TA = –40؇C to +85؇C
Units
Description
t16 10
t17 10
t18 25
t19 20
t20 50
t21 10
t22 10
ns min
ns min
ns min
ns min
ns max
ns typ
ns typ
AUX DATA Setup Time
AUX DATA Hold Time
AUX LATCH to SCLK Falling Edge Setup Time
AUX LATCH to SCLK Falling Edge Hold Time
AUX LATCH High to AUX FLAG Valid Delay
Digital Output Rise Time
Digital Output Fall Time
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t13 specifies a window, that Tx SLEEP should be asserted for the current Tx CLK to be the last prior to entering SLEEP mode.
3Digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 V.
Specifications subject to change without notice.
CLK1, CLK2,
AUX CLK
t1
t2
t3
Figure 1. Clock Timing
1.6mA IOL
TO OUTPUT
PIN
CL
15pF
+2.1V
200µA IOH
Figure 2. Load Circuit for Timing Specifications
–6– REV. B

6 Page









AD7002 pdf, datenblatt
AD7002
The offset registers have enough resolution to hold the value of
any dc offset between ± 5 V. However, the performance of the
sigma-delta modulators will degrade if full scale signals with
more than 100 mV of offset are experienced. If large offsets are
present, these can be calibrated out, but signal excursions from
the offsets should be limited to keep the I Rx and Q Rx voltages
within ± 1.35 V of VREF.
Receive Section Digital Interface
A flexible serial interface is provided for the AD7002 receive
section. Four basic operating modes are available. Table II
shows the truth table for the different serial modes available.
The MODE pin determines whether the I and Q serial data is
made available on two separate pins (MODE 1) or combined
onto a single output pin (MODE 0). The RATE pin determines
whether I and Q receive data is provided at 541.7 kHz (RATE 1)
or at 270.8 kHz (RATE 0).
When the receive section is put into sleep mode, by bringing
Rx SLEEP1 and Rx SLEEP2 high, the receive interface will
complete the current IQ cycle before entering into a low power
sleep mode.
MODE 0 RATE I Interface
The timing diagram for the MODE 0 RATE 1 receive interface
is shown in Figure 16. It can be used to interface to DSP pro-
cessors requiring only one serial port.
When using MODE 0, the serial data is made available on the
Rx DATA pin, with the I/Q pin indicating whether the 12-bit
word being clocked out is an I sample or a Q sample. Although
the I data is clocked out before the Q data, internally both
samples are processed together. RATE 1 selects an output word
rate of 541.7 kHz, which is equal to the master clock (CLK1,
CLK2) divided by 24.
When the receive section is brought out of sleep mode, by bring-
ing Rx SLEEP1 and Rx SLEEP2 low, (after 32 master clock
cycles) the Rx CLK output will continuously shift out I and Q
data, always beginning with I data. Rx SYNC provides a fram-
ing signal used to indicate the beginning of an I or Q, 12-bit
data word that is valid on the next falling edge of Rx CLK. On
coming out of sleep, Rx SYNC goes high one clock cycle before
the beginning of I data, and subsequently goes high in the same
clock cycle as the last bit of each 12-bit word (both I and Q). Rx
DATA is valid on the falling edge of Rx CLK and is clocked out
MSB first, with the I/Q pin indicating whether Rx DATA is I
data or Q data.
MODE 0 RATE 0 Interface
Figure 17 shows the receive timing diagram when MODE 0,
RATE 0 is selected. Again I and Q data are shifted out on the
Rx DATA pin, but here the output word rate is reduced to
270.8 kHz, this being equal to master clock (CLK1, CLK2)
divided by 48.
Once the receive section is brought out of sleep mode, (after 56
master clock cycles) the Rx CLK output becomes active and
generates an Rx SYNC framing pulse on the first Rx CLK.
This is followed by 12 continuous clock cycles during which the
I data is shifted out on the Rx DATA pin. Following this the
Rx CLK remains high for 11 master clock cycles before clocking
out the Q data in exactly the same manner.
Rx DATA is valid on the falling edge of Rx CLK with the I/Q
pin indicating whether Rx DATA is I data or Q data.
MODE 1 RATE I Interface
Figure 18 shows the timing for MODE 1 RATE 1 receive digital
interface. MODE 1 RATE 1 gives an output word rate of
541.7 kHz, but I and Q data are transferred on separate pins.
I data is shifted out on Rx DATA (IDATA) pin and Q data is
shifted out on the I/Q (QDATA) pin. RATE 1 selects an output
word rate of 541.7 kHz (this is equal to the master clock divided
by 24).
When the receive section is brought out of sleep mode, by bring-
ing Rx SLEEP1 and Rx SLEEP2 low (after 32 master clock
cycles), the Rx CLK output will continuously shift out I and Q
data, on separate pins. Rx SYNC provides a framing signal used
to indicate the beginning of an I or Q, 12-bit data word that
is valid on the next falling edge of Rx CLK. On coming out
of sleep, Rx SYNC goes high one clock cycle before the begin-
ning of I data, and subsequently goes high in the same clock
cycle as the I and Q LSBs. It takes 24 Rx CLKs (excluding the
first framing pulse) to complete a single IQ cycle. IDATA and
QDATA are valid on the falling edge of Rx CLK and are
clocked out MSB first.
MODE I RATE 0 Interface
Figure 19 shows the receive timing diagram when MODE 1
RATE 0 is selected. MODE 1 RATE 0, again I and Q data are
transferred on separate pins. I data is shifted out on Rx DATA
(IDATA) pin and Q data is shifted out on the I/Q (QDATA)
pin. The output word rate is reduced to 270.8 kHz, this equal to
master clock (CLK1, CLK2) divided by 48.
Once the receive section is brought out of sleep mode, and after
56 master clock cycles, the Rx CLK output becomes active and
generates an Rx SYNC framing pulse on the first Rx CLK. This
is followed by 12 continuous clock cycles during which both the
I and Q data is shifted out on IDATA and QDATA pins. Fol-
lowing this the Rx CLK remains high for 22 master clock cycles
before clocking out the next IQ data pair.
–12–
REV. B

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