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PDF AD678 Data sheet ( Hoja de datos )
| Número de pieza | AD678 | |
| Descripción | 12-Bit 200 kSPS Complete Sampling ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
AC and DC Characterized and Specified
(K, B and T Grades)
200k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
72 dB S/N+D (K, B, T Grades)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 M⍀ Input Impedance
8-Bit or 16-Bit Bus Interface
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
Commercial, Industrial and Military Temperature
Range Grades
MIL-STD-883 Compliant Versions Available
12-Bit 200 kSPS
Complete Sampling ADC
AD678
REFOUT
REFIN
BIPOFF
AIN
AGND
FUNCTIONAL BLOCK DIAGRAM
CS SC OE EOCEN SYNC 12/8 EOC
VOLTAGE
REF.
CONTROL LOGIC
12
12
12-BIT D/A
CONVERSION
CONVERTER
LOGIC
AD678
OUTPUT
REGISTER
SAMPLE/
HOLD
GAIN
STAGE
4
4-BIT FLASH
A/D
CONVERTER
DB11
DB2
DB1
(R/L)
DB0
(HBE)
VCC
VEE
VDD
DGND
PRODUCT DESCRIPTION
The AD678 is a complete, multipurpose 12-bit monolithic
analog-to-digital converter, consisting of a sample-hold ampli-
fier (SHA), a microprocessor compatible bus interface, a voltage
reference and clock generation circuitry.
The AD678 is specified for ac (or “dynamic”) parameters such
as S/N+D ratio, THD and IMD which are important in signal
processing applications. In addition, the AD678K, B and T
grades are fully specified for dc parameters which are important
in measurement applications.
The AD678 offers a choice of digital interface formats; the 12
data bits can be accessed by a 16-bit bus in a single read opera-
tion or by an 8-bit bus in two read operations (8+4), with right
or left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of 10 V with a full power bandwidth of
1 MHz and a full linear bandwidth of 500 kHz. High input im-
pedance (10 MΩ) allows direct connection to unbuffered
sources without signal degradation.
This product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm which includes error correction and flash converter
circuitry to achieve high speed and resolution.
The AD678 operates from +5 V and ±12 V supplies and dissipates
560 mW (typ). The AD678 is available in 28-lead plastic DIP,
ceramic DIP, and 44-lead J-leaded ceramic surface mount packages.
Screening to MIL-STD-883C Class B is also available.
PRODUCT HIGHLIGHTS
1. COMPLETE INTEGRATION: The AD678 minimizes ex-
ternal component requirements by combining a high speed
sample-hold amplifier (SHA), ADC, 5 V reference, clock and
digital interface on a single chip. This provides a fully speci-
fied sampling A/D function unattainable with discrete designs.
2. SPECIFICATIONS: The AD678K, B and T grades provide
fully specified and tested ac and dc parameters. The AD678J,
A and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica-
tions (such as INL, gain and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, THD and IMD) are of value in signal process-
ing applications.
3. EASE OF USE: The pinout is designed for easy board lay-
out, and the choice of single or two read cycle output pro-
vides compatibility with 16- or 8-bit buses. Factory trimming
eliminates the need for calibration modes or external trim-
ming to achieve rated performance.
4. RELIABILITY: The AD678 utilizes Analog Devices’ mono-
lithic BiMOS technology. This ensures long-term reliability
compared to multichip and hybrid designs.
5. UPGRADE PATH: The AD678 provides the same pinout as
the 14-bit, 128 kSPS AD679 ADC.
6. The AD678 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD678/883B data sheet for detailed
specifications.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
ABSOLUTE MAXIMUM RATINGS*
Specification
With
Respect
To
Min
Max
Units
VCC
VEE
VCC
VDD
AGND
AIN, REFIN
Digital Inputs
Digital Outputs
Max Junction
Temperature
Operating Temperature
J and K Grades
A and B Grades
S and T Grades
Storage Temperature
Lead Temperature
(10 sec max)
AGND
AGND
VEE
DGND
DGND
AGND
DGND
DGND
–0.3 +18
V
–18 +0.3
V
–0.3 +26.4 V
0 +7
V
–1 +1
V
VEE VCC
–0.5 +7
V
V
–0.5 VDD + 0.3 V
175 °C
0 +70
–40 +85
–55 +125
–65 +150
°C
°C
°C
°C
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD678
REFOUT
REFIN
BIPOFF
AIN
AGND
CS SC OE EOCEN SYNC 12/8 EOC
VOLTAGE
REF.
CONTROL LOGIC
12
12
12-BIT D/A
CONVERSION
CONVERTER
LOGIC
AD678
OUTPUT
REGISTER
SAMPLE/
HOLD
GAIN
STAGE
4
4-BIT FLASH
A/D
CONVERTER
DB11
DB2
DB1
(R/L)
DB0
(HBE)
VCC
VEE
VDD
DGND
Functional Block Diagram
ESD SENSITIVITY
The AD678 features input protection circuitry consisting of large “distributed” diodes and polysilicon
series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy
pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD678 has been
classified as a Category 1 device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment
and discharge without detection. Unused devices must be stored in conductive foam or shunts, and
the foam should be discharged to the destination socket before devices are removed. For further
information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model1
Package
Temperature Range
Tested and Specified
Package Option2
AD678JN
AD678KN
AD678JD
AD678KD
AD678AD
AD678BD
AD678AJ
AD678BJ
AD678SD
AD678TD
28-Lead Plastic DIP
28-Lead Plastic DIP
28-Lead Ceramic DIP
28-Lead Ceramic DIP
28-Lead Ceramic DIP
28-Lead Ceramic DIP
44-Lead Ceramic JLCC
44-Lead Ceramic JLCC
28-Lead Ceramic DIP
28-Lead Ceramic DIP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
AC
AC + DC
AC
AC + DC
AC
AC + DC
AC
AC + DC
AC
AC + DC
N-28
N-28
D-28
D-28
D-28
D-28
J-44
J-44
D-28
D-28
NOTES
1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to Analog Devices Military Products Databook or /883 data sheet.
2N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.
REV. C
–5–
5 Page 
AD678
A single-pass calibration can be done by substituting a bipolar
offset trim (error at minus full scale) for the bipolar zero trim
(error at midscale), using the same circuit. First, apply a signal
1/2 LSB above minus full scale (–4.9988 V for a ± 5 V range)
and adjust R1 until the minus full-scale transition is located
(1000 0000 0000 to 1000 0000 0001). Then perform the gain
error trim as outlined above.
The AD678 incorporates several features to help the user’s
layout. Analog pins (VEE) AIN, AGND, REFOUT, REFIN,
BIPOFF, VCC) are adjacent to help isolate analog from digital
signals. In addition, the 10 MΩ input impedance of AIN mini-
mizes input trace impedance errors. Finally, ground currents
have been minimized by careful circuit design. Current through
AGND is 200 µA, with no code-dependent variation. The cur-
rent through DGND is dominated by the return current for
DB11–DB0 and EOC.
Figure 12. Unipolar Input Connections with Gain and
Offset Trims
SUPPLY DECOUPLING
The AD678 power supplies should be well filtered, well regulated,
and free from high-frequency noise. Switching power supplies
are not recommended. These supplies generate spikes which can
induce noise in the analog system.
Decoupling capacitors should be located as close as possible to
all power supply pins. A 10 µF tantalum capacitor in parallel
with a 0.1 µF ceramic provides adequate decoupling. The power
supply pins should be decoupled directly to AGND.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD678, associated analog input circuitry and interconnec-
tions as far as possible from logic circuitry. A solid analog ground
plane around the AD678 will isolate large switching ground
currents. For these reasons, the use of wire wrap circuit con-
struction is not recommended; careful printed circuit construction
is preferred.
Figure 13. Bipolar Input Connections with Gain and Offset
Trims
BOARD LAYOUT
Designing with high-resolution data converters requires careful
attention to layout. Trace impedance is a significant issue. At the
12-bit level, a 5 mA current through a 0.5 Ω trace will develop a
voltage drop of 2.5 mV, which is 1 LSB for a 10 V full-scale span.
In addition to ground drops, inductive and capacitive coupling
need to be considered, especially when high- accuracy analog
signals share the same board with digital signals. Finally, power
supplies need to be decoupled in order to filter out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single inter-
connection point to minimize ground loops. Analog signals should
be routed as far as possible from digital signals and should cross
them at right angles.
GROUNDING
If a single AD678 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD678. If multiple AD678s are used or the AD678 shares ana-
log supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This prevents large ground loops which inductively
couple noise and allow digital currents to flow through the ana-
log system.
INTERFACING THE AD678 TO MICROPROCESSORS
The I/O capabilities of the AD678 allow direct interfacing to
general purpose and DSP microprocessor buses. The asynchro-
nous conversion control feature allows complete flexibility and
control with minimal external hardware.
The following examples illustrate typical AD678 interface
configurations.
REV. C
–11–
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AD678.PDF ] | |
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