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AD676 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD676
Beschreibung 16-Bit 100 kSPS Sampling ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD676 Datasheet, Funktion
a
16-Bit 100 kSPS
Sampling ADC
FEATURES
Autocalibrating
On-Chip Sample-Hold Function
Parallel Output Format
16 Bits No Missing Codes
؎1 LSB INL
–97 dB THD
90 dB S/(N+D)
1 MHz Full Power Bandwidth
AD676
FUNCTIONAL BLOCK DIAGRAM
VIN 15
AGND SENSE 14
VREF 16
AGND 13
INPUT
BUFFERS
16-BIT
DAC
CAL
DAC
ANALOG
CHIP
COMP
LOGIC & TIMING
LEVEL TRANSLATORS
PRODUCT DESCRIPTION
The AD676 is a multipurpose 16-bit parallel output analog-to-
digital converter which utilizes a switched-capacitor/charge
redistribution architecture to achieve a 100 kSPS conversion
rate (10 µs total conversion time). Overall performance is opti-
mized by digitally correcting internal nonlinearities through
on-chip autocalibration.
The AD676 circuitry is segmented onto two monolithic chips—
a digital control chip fabricated on Analog Devices DSP CMOS
process and an analog ADC chip fabricated on our BiMOS II
process. Both chips are contained in a single package.
The AD676 is specified for ac (or “dynamic”) parameters such
as S/(N+D) Ratio, THD and IMD which are important in sig-
nal processing applications. In addition, dc parameters are
specified which are important in measurement applications.
DIGITAL
CHIP
CAL 8
SAMPLE 9
CLK 10
MICRO-CODED
CONTROLLER
SAR
PAT
GEN
ALU
RAM
7 BUSY
1
L
A6
T BIT 1 – BIT 16
C 19
H 28
AD676
The AD676 operates from +5 V and ± 12 V supplies and typi-
cally consumes 360 mW during conversion. The digital supply
(VDD) is separated from the analog supplies (VCC, VEE) for re-
duced digital crosstalk. An analog ground sense is provided for
the analog input. Separate analog and digital grounds are also
provided.
The AD676 is available in a 28-pin plastic DIP or 28-pin side-
brazed ceramic package. A serial-output version, the AD677, is
available in a 16-pin 300 mil wide ceramic or plastic package.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD676 Datasheet, Funktion
AD676
Pin Name
Type
1–6 BIT 11-BIT 16 DO
7 BUSY
DO
8 CAL
9 SAMPLE
DI
DI
10 CLK
DI
11 DGND
P
12 VCC
13 AGND
P
P/AI
14 AGND SENSE AI
15 VIN
16 VREF
17 VEE
AI
AI
P
18 VDD
19–28 BIT 1–BIT 10
Type: AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
P
DO
PIN DESCRIPTION
Description
BIT 11–BIT 16 represent the six LSBs of data.
Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress.
BUSY should be buffered when capacitively loaded.
Calibration Control Pin (Asynchronous).
VIN Acquisition Control Pin. Active HIGH. During conversion, SAMPLE controls the state
of the internal sample-hold amplifier and the falling edge initiates conversion (see “Conver-
sion Control” paragraph). During calibration, SAMPLE should be held LOW. If HIGH dur-
ing calibration, diagnostic information will appear on the two LSBs (Pins 5 and 6).
Master Clock Input. The AD676 requires 17 clock cycles to execute a conversion.
Digital Ground.
+12 V Analog Supply Voltage.
Analog Ground.
Analog Ground Sense.
Analog Input Voltage.
External Voltage Reference Input.
–12 V Analog Supply Voltage. Note: the lid of the ceramic package is internally connected to
VEE.
+5 V Logic Supply Voltage.
BIT 1–BIT 10 represent the ten MSB of data.
BIT 11 1
BIT 12 2
BIT 13 3
BIT 14 4
BIT 15 5
BIT 16 (LSB) 6
BUSY 7
CAL 8
SAMPLE 9
CLK 10
DGND 11
VCC 12
AGND 13
AGND SENSE 14
AD676
TOP VIEW
(Not to Scale)
28 BIT 10
27 BIT 9
26 BIT 8
25 BIT 7
24 BIT 6
23 BIT 5
22 BIT 4
21 BIT 3
20 BIT 2
19 BIT 1 (MSB)
18 VDD
17 VEE
16 VREF
15 VIN
Package Pinout
VIN 15
AGND SENSE 14
VREF 16
AGND 13
INPUT
BUFFERS
16-BIT
DAC
CAL
DAC
ANALOG
CHIP
COMP
LOGIC & TIMING
LEVEL TRANSLATORS
DIGITAL
CHIP
CAL 8
SAMPLE 9
CLK 10
MICRO-CODED
CONTROLLER
SAR
PAT
GEN
ALU
RAM
7 BUSY
1
L
A6
T BIT 1 – BIT 16
C 19
H 28
AD676
Functional Block Diagram
–6– REV. A

6 Page









AD676 pdf, datenblatt
AD676
AD586 output, thereby optimizing the overall performance of
the AD676. It is recommended that a 10 µF to 47 µF high qual-
ity tantalum capacitor be tied between the VREF input of the
AD676 and ground to minimize the impedance on the
reference.
10
10µF
0.1µF
AD587
2 VIN
VO 6
GND
4
NR 8
1µF
+15V
100µF
+5V
100µF
–15V
100µF
78L12
79L12
10
0.01µF 10µF
10
0.1µF
10
0.01µF
0.1µF
12
VCC
VREF 16
18 VDD AD676
VEE VIN
17 15
10µF
0.1µF
10µF
VIN
Figure 7.
Using the AD676 with ± 10 V input range (VREF = 10 V) typi-
cally requires ± 15 V supplies to drive op amps and the voltage
reference. If ± 12 V is not available in the system, regulators
such as 78L12 and 79L12 can be used to provide power for the
AD676. This is also the recommended approach (for any input
range) when the ADC system is subjected to harsh environ-
ments such as where the power supplies are noisy and where
voltage spikes are present. Figure 7 shows an example of such a
system based upon the 10 V AD587 reference, which provides a
300 µV LSB. Circuitry for additional protection against power
supply disturbances has been shown. A 100 µF capacitor at each
regulator prevents very large voltage spikes from entering the
regulators. Any power line noise which the regulators cannot
eliminate will be further filtered by an RC filter (10 /10 µF)
having a –3 dB point at 1.6 kHz. For best results the regulators
should be within a few centimeters of the AD676.
ANALOG INPUT
As previously discussed, the analog input voltage range for the
AD676 is ± VREF. For purposes of ground drop and common
mode rejection, the VIN and VREF inputs each have their own
ground. VREF is referred to the local analog system ground
(AGND), and VIN is referred to the analog ground sense pin
(AGND SENSE) which allows a remote ground sense for the
input signal.
The AD676 analog inputs (VIN, VREF and AGND SENSE) ex-
hibit dynamic characteristics. When a conversion cycle begins,
each analog input is connected to an internal, discharged 50 pF
capacitor which then charges to the voltage present at the corre-
sponding pin. The capacitor is disconnected when SAMPLE is
taken LOW, and the stored charge is used in the subsequent
conversion. In order to limit the demands placed on the external
source by this high initial charging current, an internal buffer
amplifier is employed between the input and this capacitance for
a few hundred nanoseconds. During this time the input pin ex-
hibits typically 20 kinput resistance, 10 pF input capacitance
and ± 40 µA bias current. Next, the input is switched directly to
the now precharged capacitor and allowed to fully settle. During
this time the input sees only a 50 pF capacitor. Once the sample
is taken, the input is internally floated so that the external input
source sees a very high input resistance and a parasitic input ca-
pacitance of typically only 2 pF. As a result, the only dominant
input characteristic which must be considered is the high cur-
rent steps which occur when the internal buffers are switched in
and out.
In most cases, these characteristics require the use of an external
op amp to drive the input of the AD676. Care should he taken
with op amp selection; even with modest loading conditions,
most available op amps do not meet the low distortion require-
ments necessary to match the performance capabilities of the
AD676. Figure 8 represents a circuit, based upon the AD845,
recommended for low noise, low distortion ac applications.
For applications optimized more for low bias and low offset than
speed or bandwidth, the AD845 of Figure 8 may be replaced by
the OP27.
1k
±5V
INPUT
1k
499
+12V
0.1µF
27
AD845
34
6
0.1µF
AD676
15 VIN
–12V
13 AGND
14 AGND
SENSE
Figure 8.
–12–
REV. A

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