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AD668 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD668
Beschreibung 12-Bit Ultrahigh Speed Multiplying D/A Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD668 Datasheet, Funktion
a
FEATURES
Ultrahigh Speed: Current Settling to 1 LSB in 90 ns for
a Full-Scale Change in Digital Input. Voltage Settling
to 1 LSB in 120 ns for a Full-Scale Change in Analog
Input
15 MHz Reference Bandwidth
Monotonicity Guaranteed over Temperature
10.24 mA Current Output or 1.024 V Voltage Output
Integral and Differential Linearity Guaranteed over
Temperature
0.3" “Skinny DIP” Packaging
MIL-STD-883 Compliant Versions Available
12-Bit Ultrahigh Speed
Multiplying D/A Converter
AD668
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD668 is an ultrahigh speed, 12-bit, multiplying digital-to-
analog converter, providing outstanding accuracy and speed per-
formance in responding to both analog and digital inputs. The
AD668 provides a level of performance and functionality in a
monolithic device that exceeds that of many contemporary hy-
brid devices. The part is fabricated using Analog Devices’
Complementary Bipolar (CB) Process, which features vertical
NPN and PNP devices on the same chip without the use of
dielectric isolation. The AD668’s design capitalizes on this pro-
prietary process in combination with standard low impedance
circuit techniques to provide its unique combination of speed
and accuracy in a monolithic part.
The wideband reference input is buffered by a high gain, closed
loop reference amplifier. The reference input is essentially a 1 V,
high impedance input, but trimmed resistive dividers are pro-
vided to readily accommodate 5 V and 1.25 V references. The
reference amplifier features an effective small signal bandwidth
of 15 MHz and an effective slew rate of 3% of full scale/ns.
Multiple matched current sources and thin film ladder tech-
niques are combined to produce bit weighting. The output range
can nominally be taken as a 10.24 mA current output or a 1.024 V
voltage output. Varying the analog input can provide modulation
of the DAC full scale from 10% to 120% of its nominal value.
Bipolar outputs can be realized through pin-strapping to provide
two-quadrant operation without additional external circuitry.
Laser wafer trimming insures full 12-bit linearity and excellent
gain accuracy. All grades of the AD668 are guaranteed mono-
tonic over their full operating temperature range. Furthermore,
the output resistance of the DAC is trimmed to 100 Ω ± 1.0%.
The AD668 is available in four performance grades. The
AD668JQ and KQ are specified for operation from 0°C to
+70°C, the AD668AQ is specified for operation from –40°C to
+85°C, and the AD668SQ specified for operation from –55°C
to +125°C. All grades are available in a 24-pin cerdip (0.3"
package.
PRODUCT HIGHLIGHTS
1. The fast settling time of the AD668 provides suitable perfor-
mance for waveform generation, graphics display, and high
speed A/D conversion applications.
2. The high bandwidth reference channel allows high frequency
modulation between analog and digital inputs.
3. The AD668’s design is configured to allow wide variation of
the analog input, from 10% to 120% of its nominal value.
4. The AD668’s combination of high performance and tremen-
dous flexibility makes it an ideal building block for a variety
of high speed, high accuracy instrumentation applications.
5. The digital inputs are readily compatible with both TTL and
5 V CMOS logic families.
6. Skinny DIP (0.3") packaging minimizes board space require-
ments and eases layout considerations.
7. The AD668 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD668/883B data sheet for detailed
specifications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD668 Datasheet, Funktion
AD668
0.1 < V IN < 1.2
V NOM
0 < VIN/VNOM < 0.1 constitutes an undervoltage condition and
is subject to the specified recovery time.
1.2 < VIN/VNOM constitutes an overvoltage condition. This can
saturate the DAC transistors, resulting in decreased response
time and can, over extended time, damage the part through ex-
cessive power dissipation. Figure 3 indicates the specified re-
gions of operation in both the unipolar and bipolar cases.
The small signal 3 dB bandwidth of the VIN channel is 15 MHz.
The large signal 3 dB bandwidth is approximately 10 MHz.
VOUT is limited by the specified output compliance: –2 V to
+1.2 V.
OUTPUT VOLTAGE COMPLIANCE
The AD668 has an output compliance range of –2.0 V to
+1.2 V (with respect to the LCOM pin). The current steering
output stages will be unaffected by changes in the output termi-
nal voltage over this range. However, as shown in Figure 4,
there is an equivalent output impedance of 200 in parallel
with 15 pF at the output terminal, producing an equivalent er-
ror current if the voltage deviates from the ladder common.
This is a linear effect which does not change with input code.
Operation beyond the maximum compliance limits may cause
either output stage saturation or breakdown, resulting in non-
linear performance. The positive compliance limit is not af-
fected by the positive power supply, but is a function of the
output current and the logic threshold voltage at VTH, Pin 13.
Figure 3. Quadrant Plots of the AD668
CIRCUIT DESCRIPTION OF THE AD668
Successful design of high speed, high resolution systems de-
mands a designer’s solid working knowledge of the components
being used. The AD668 has been carefully configured to pro-
vide maximum functionality in a variety of applications. While it
is beyond the scope of this data sheet to exhaustively cover each
potential application topology, the detailed information that
follows is intended to provide the designer with a sufficiently
thorough understanding of the part’s inner workings to allow
selection of the circuit topology to best suit the application.
CURRENT OUTPUT VS. VOLTAGE-OUTPUT
As indicated in the FUNCTIONAL DESCRIPTION, the
AD668 output may be taken as either a voltage or a current,
depending on external circuit connections. In the current output
mode, the DAC output (Pin 20) is tied to a summing junction,
and the current flowing from the DAC into this summing junc-
tion is sensed. In this mode, the DAC output scale is insensitive
to whether the load resistor, RLOAD, is shorted (Pin 19 con-
nected to Pin 20), or grounded (Pin 19 connected to Pin 18).
However, the connection of this resistor does affect the output
impedance of the DAC and may have a significant impact on
the noise gain and stability of the external circuitry. Grounding
RLOAD will reduce the output impedance, thereby increasing the
noise gain and also enhancing the stability of a circuit using a
non-unity-gain-stable op amp (see Figure 10).
In the voltage output mode, the DAC’s output current flows
through its own internal impedance (perhaps in parallel with an
external impedance) to generate a voltage. In this case, the DAC
output scale is directly dependent on the load impedance. The
temperature coefficient of the AD668’s transfer function will be
lowest when used in the voltage output mode.
Figure 4. Equivalent Output Circuit
ANALOG INPUT CONSIDERATIONS
The reference input buffer can be viewed as a resistive divider
connected to one terminal of an op amp, as shown in Figure 5.
A unit DAC current source drives a resistor to produce a voltage
that is fed back to the opposite terminal of the op amp. Resistor
RFEEDBACK is laser-trimmed to ensure that a 1 V input to node A of
the op amp will produce a 10.24 mA DAC output. REFIN1 and
REFIN2 may be configured in any way the user chooses to pro-
vide a nominal input full scale of 1 V at node A. R1 and R2 are
sized and trimmed to provide both a 5:1 voltage divider and a
parallel impedance that matches the impedance at node B,
thereby reducing the amplifier offset voltage due to bias current.
The resistive divider is trimmed with an external 50 resistor in
series with the 4k leg (R2). This provides a gain trim range of±1%
using a 100 trim potentiometer (Figure 7). If trimming is not
desired, a 50 resistor may be used in place of the potentiom-
eter to produce the specified gain accuracy, or the resistor may
be omitted altogether to produce a nominal gain error of +1%.
Figure 5. Equivalent Analog Input Circuitry
–6– REV. A

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AD668 pdf, datenblatt
AD668
HIGH SPEED INTERCONNECT AND ROUTING
It is essential that care be taken in the signal and power ground
circuits to avoid inducing extraneous voltage drops in the signal
ground paths. It is suggested that all connections be short, di-
rect, and as physically close to the package as possible, thereby
minimizing the sharing of conduction paths between different
currents. When runs exceed an inch or so in length, some type
of termination resistor may be required. The necessity and value
of this resistor will be dependent upon the logic family used.
For maximum ac performance, the DAC should be mounted di-
rectly to the circuit board; sockets should be avoided as they in-
troduce unwanted capacitive coupling between adjacent pins of
the device. For purposes of testing and characterization, low
profile sockets are preferable to zero insertion force types.
TYPICAL PERFORMANCE CHARACTERISTICS
The following plots indicate the typical performance of the
AD668 in properly configured circuits. Wherever possible, sug-
gestions are provided to assist the user in achieving the indicated
performance levels.
DC PERFORMANCE
Power Consumption vs. VREF/VNOM
As suggested in previous sections, most portions of AD668’s
current budget are proportional to the analog input signal. As a
result, operating the part at a reduced reference voltage offers
substantial power savings. This may be particularly attractive in
applications featuring a buffered output voltage, since the size of
the feedback resistor may be increased to compensate for the re-
duced DAC current. For example, the DAC could be config-
ured in the 5 V input mode, but driven with a 2.5 V reference,
producing a 5.12 mA full scale output. Reducing the output
level has performance ramifications in several areas, as demon-
strated later in this section, but the circuit designer is free to
trade power dissipation against performance to optimize the
AD668 for his application.
Figure 16. Linearity vs. Reference Level
AC PERFORMANCE
For the purposes of characterizing the frequency domain perfor-
mance of the AD668, all bits are turned on and the DAC is es-
sentially treated as a voltage amplifier/attenuator. The tests used
to generate these performance curves were done using the cir-
cuit shown in Figure 12.
AC characterization in the megahertz region is not trivial, and
special consideration is required to produce meaningful results.
Probe ground straps are inappropriate at these frequencies;
some type of probe socket is required. Signals should be routed
either on a PC board over a ground plane or through a coaxial
cable. Proper termination impedances should be used through-
out the fixturing.
Large Signal Frequency Response
Figure 17 represents the gain and phase response of a signal
swinging from 10% to 120% (peak to peak) of the nominal ref-
erence input. The DAC reference amplifier has an effective slew
rate or 30 V/µs at the DAC output, so there will be slew-induced
distortion for full scale swings at greater than 10 MHz.
Figure 15. Power Consumption vs. Reference Level
Linearity vs. VREF/VNOM
At reduced current levels, the linearity of the PNP DAC used in
the AD668 becomes more sensitive to the mismatch in transis-
tor VBE’s. As Figure 16 indicates, this effect starts to increase
fairly dramatically for reference levels less than 25% of nominal.
Increasing the current level above 100% does not appreciably
improve the linearity performance since the DAC has been
trimmed to perform optimally at the 100% reference level.
Figure 17. Large Signal Gain and Phase Response
Small Signal 3 dB Bandwidth vs. VREF/VNOM
Figure 18 demonstrates the small signal (20% of nominal refer-
ence) bandwidth sensitivity to the analog input’s dc bias. The
small signal 3 dB bandwidth at 100% reference levels is greater
than 15 MHz, but the bandwidth remains greater than 10 MHz
over the entire nominal reference range. The differential gain
and phase for a 200 mV, 3 MHz signal are 0.5% and 2°,
respectively.
–12–
REV. A

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