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What is AD6623?

This electronic component, produced by the manufacturer "Analog Devices", performs the same function as "4-Channel/ 104 MSPS Digital Transmit Signal Processor TSP".


AD6623 Datasheet PDF - Analog Devices

Part Number AD6623
Description 4-Channel/ 104 MSPS Digital Transmit Signal Processor TSP
Manufacturers Analog Devices　
Logo Analog Devices Logo　


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a
4-Channel, 104 MSPS Digital
Transmit Signal Processor (TSP)
AD6623
FEATURES
Pin Compatible to the AD6622
18-Bit Parallel Digital IF Output
Real or Interleaved Complex
18-Bit Bidirectional Parallel Digital IF Input/Output
Allows Cascade of Chips for Additional Channels
Clipped or Wrapped Over Range
Two’s Complement or Offset Binary Output
Four Independent Digital Transmitters in Single Package
RAM Coefficient Filter (RCF)
Programmable IF and Modulation for Each Channel
Programmable Interpolating RAM Coefficient Filter
p/4-DQPSK Differential Phase Encoder
3p/8-PSK Linear Encoder
8-PSK Linear Encoder
Programmable GMSK Look-Up Table
Programmable QPSK Look-Up Table
All-Pass Phase Equalizer
Programmable Fine Scaler
Programmable Power Ramp Unit
High Speed CIC Interpolating Filter
Digital Resampling for Noninteger Interpolation Rates
NCO Frequency Translation
Spurious Performance Better than –100 dBc
Separate 3-Wire Serial Data Input for Each Channel
Bidirectional Serial Clocks and Frames
Microprocessor Control
2.5 V CMOS Core, 3.3 V Outputs, 5 V Inputs
JTAG Boundary Scan
APPLICATIONS
Cellular/PCS Base Stations
Micro/Pico Cell Base Stations
Wireless Local Loop Base Stations
Multicarrier, Multimode Digital Transmit
GSM, EDGE, IS136, PHS, IS95, TDS CDMA, UMTS,
CDMA2000
Phased Array Beam Forming Antennas
Software Defined Radio
Tuning Resolution Better than 0.025 Hz
Real or Complex Outputs
FUNCTIONAL BLOCK DIAGRAM
SDINA
SDFIA
SDFOA
SCLKA
SDINB
SDFIB
SDFOB
SCLKB
SDINC
SDFIC
SDFOC
SCLKC
SDIND
SDFID
SDFOD
SCLKD
NCO = NUMERICALLY CONTROLLED
OSCILLATOR/TUNER
SPORT
DATA
RAM
I
COEFFICIENT Q
FILTER
SCALER I
AND Q
POWER
RAMP
I
CIC5
FILTER
Q
I
RCIC2
FILTER
Q
CHAN A
NCO
QIN
IN
[17–0]
SPORT
DATA
RAM
I
COEFFICIENT Q
FILTER
SCALER I
AND Q
POWER
RAMP
I
CIC5
FILTER
Q
I
RCIC2
FILTER
Q
SPORT
DATA
RAM
I
COEFFICIENT Q
FILTER
SCALER I
AND Q
POWER
RAMP
I
CIC5
FILTER
Q
I
RCIC2
FILTER
Q
SPORT
DATA
RAM
I
COEFFICIENT Q
FILTER
SCALER I
AND Q
POWER
RAMP
I
CIC5
FILTER
Q
I
RCIC2
FILTER
Q
CHAN B
NCO
SUMMATION
CHAN C
NCO
SYNC
4
CHAN D
NCO
OEN
QOUT
OUT
[17:0]
JTAG
MICROPORT
REV. 0
TDL TDO TMS TCK TRST
D[7:0] DS DTACK RW MODE A[2:0] CS
CLK RESET
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002

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AD6623 equivalent
GENERAL TIMING CHARACTERISTICS1, 2
Parameter (Conditions)
Temp
Test
Level
AD6623AS
Min Typ Max
CLK Timing Requirements:
tCLK
tCLKL
tCLKH
CLK Period
CLK Width Low
CLK Width High
RESET Timing Requirement:
tRESL
RESET Width Low
Full I
Full IV
Full IV
Full I
9.6
3
3
30.0
0.5 × tCLK
Input Data Timing Requirements:
tSI INOUT[17:0], QIN to ↑CLK Setup Time Full IV
tHI INOUT[17:0], QIN to ↑CLK Hold Time Full IV
Output Data Timing Characteristics:
tDO ↑CLK to OUT[17:0], INOUT[17:0],
QOUT Output Delay Time
tDZO OEN HIGH to OUT[17:0] Active
Full IV
Full IV
1
2
2
3
6
7.5
SYNC Timing Requirements:
tSS SYNC(0, 1, 2, 3) to ↑CLK Setup Time
tHS SYNC(0, 1, 2, 3) to ↑CLK Hold Time
Full IV
Full IV
1
2
Master Mode Serial Port Timing Requirements (SCS = 0):
Switching Characteristics3
tDSCLK1
tDSCLKH
tDSCLKL
↑CLK to ↑SCLK Delay (divide by 1)
↑CLK to ↑SCLK Delay (for any other divisor)
↑CLK to ↓SCLK Delay
(divide by 2 or even number)
tDSCLKLL
↓CLK to ↓SCLK Delay
(divide by 3 or odd number)
Channel is Self-Framing
tSSDI0
tHSDI0
tDSFO0A
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↑SCLK to SDFO Delay
Channel is External-Framing
tSSFI0
tHSFI0
tSSDI0
tHSDI0
tDSFO0B
SDFI to ↑SCLK Setup Time
SDFI to ↑SCLK Hold Time
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↑SCLK to SDFO Delay
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
4
5
3.5
4
1.7
0
0.5
2
0
2
0
0.5
Slave Mode Serial Port Timing Requirements (SCS = 1):
Switching Characteristics3
tSCLK
tSCLKL
tSCLKH
SCLK Period
SCLK Low Time
SCLK High Time
Channel is Self-Framing
Full IV
Full IV
Full IV
3.5
3.5
tSSDH
tHSDH
tDSFO1
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↑SCLK to SDFO Delay
Channel is External-Framing
Full IV
Full IV
Full IV
1
2.5
4
tSSFI1
tHSFI1
tSSDI1
tHSDI1
tDSFO1
SDFI to ↑ SCLK Setup Time
SDFI to ↑SCLK Hold Time
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↓SCLK to SDFO Delay
Full IV
Full IV
Full IV
Full IV
Full IV
2
1
1
2.5
10
NOTES
1All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
2CLOAD = 40 pF on all outputs (unless otherwise specified).
3The timing parameters for SCLK, SDIN, SDFI, SDFO, and SYNC apply to all four channels (A, B, C, and D).
Specifications subject to change without notice.
10.5
13
9
10
3.5
3
2 ؋ tCLK
10
AD6623
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0
–5–


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Part Details

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