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PDF AD654 Data sheet ( Hoja de datos )
| Número de pieza | AD654 | |
| Descripción | Low Cost Monolithic Voltage-to-Frequency Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Low Cost
Single or Dual Supply, 5 V to 36 V, ؎5 V to ؎18 V
Full-Scale Frequency Up to 500 kHz
Minimum Number of External Components Needed
Versatile Input Amplifier
Positive or Negative Voltage Modes
Negative Current Mode
High Input Impedance, Low Drift
Low Power: 2.0 mA Quiescent Current
Low Offset: 1 mV
Low Cost Monolithic
Voltage-to-Frequency Converter
AD654
FUNCTIONAL BLOCK DIAGRAM
+VS
CT
87
CT –VS
65
DRIVER
OSC
AD654
1
FOUT
2
LOGIC
COMMON
3
RT
4
+VIN
PRODUCT DESCRIPTION
The AD654 is a monolithic V/F converter consisting of an input
amplifier, a precision oscillator system, and a high current output
stage. A single RC network is all that is required to set up any
full scale (FS) frequency up to 500 kHz and any FS input voltage
up to ± 30 V. Linearity error is only 0.03% for a 250 kHz FS,
and operation is guaranteed over an 80 dB dynamic range. The
overall temperature coefficient (excluding the effects of external
components) is typically ± 50 ppm/°C. The AD654 operates from
a single supply of 5 V to 36 V and consumes only 2.0 mA quies-
cent current.
The low drift (4 µV/°C typ) input amplifier allows operation
directly from small signals such as thermocouples or strain gauges
while offering a high (250 MΩ) input resistance. Unlike most
V/F converters, the AD654 provides a square-wave output, and
can drive up to 12 TTL loads, optocouplers, long cables, or
similar loads.
PRODUCT HIGHLIGHTS
1. Packaged in both an 8-lead mini-DIP and an 8-lead SOIC
package, the AD654 is a complete V/F converter requiring
only an RC timing network to set the desired full-scale fre-
quency and a selectable pull-up resistor for the open-collector
output stage. Any full scale input voltage range from 100 mV
to 10 volts (or greater, depending on +VS) can be accommo-
dated by proper selection of the timing resistor. The full-
scale frequency is then set by the timing capacitor from the
simple relationship, f = V/10 RC.
2. A minimum number of low cost external components are
necessary. A single RC network is all that is required to set
up any full scale frequency up to 500 kHz and any full-scale
input voltage up to ± 30 V.
3. Plastic packaging allows low cost implementation of the
standard VFC applications: A/D conversion, isolated signal
transmission, F/V conversion, phase-locked loops, and tuning
switched-capacitor filters.
4. Power supply requirements are minimal; only 2.0 mA of
quiescent current is drawn from the single positive supply
from 4.5 volts to 36 volts. In this mode, positive inputs can
vary from 0 volts (ground) to (+VS –4) volts. Negative inputs
can easily be connected for below ground operation.
5. The versatile open-collector output stage can sink more than
10 mA with a saturation voltage less than 0.4 volts. The Logic
Common terminal can be connected to any level between
ground (or –VS) and 4 volts below +VS. This allows easy
direct interface to any logic family with either positive or
negative logic levels.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
AD654
(OPTIONAL)
C
AD654
RCOMP
R1 R2
VIN
Figure 3b. Bias Current Compensation—Negative Inputs
If the AD654’s 1 mV offset voltage must be trimmed, the trim
must be performed external to the device. Figure 3c shows an
optional connection for positive inputs in which ROFF1 and
ROFF2 add a variable resistance in series with RT. A variable
source of ± 0.6 V applied to ROFF1 then adjusts the offset ± 1 mV.
Similarly, a ± 0.6 V variable source is applied to ROFF in Fig-
ure 3d to trim offset for negative inputs. The ±0.6 V bipolar
source could simply be an AD589 reference connected as shown
in Figure 3e.
10k⍀
VIN
ROFF2
20⍀ 5k⍀ 8.25k⍀
AD654
ROFF1
10k⍀
؎0.6V
Figure 3c. Offset Trim Positive Input (10 V FS)
؎0.6V
ROFF
5.6M⍀
10k⍀
AD654
8.25k⍀ 5k⍀
VIN
Figure 3d. Offset Trim Negative Input (–10 V FS)
R1
10k⍀
+5V
+
AD589
–
R2
10k⍀
–5V
R3
10k⍀
R4
10k⍀
R5
100k⍀
؎0.6V
Figure 3e. Offset Trim Bias Network
FULL-SCALE CALIBRATION
Full-scale trim is the calibration of the circuit to produce the
desired output frequency with a full-scale input applied. In most
cases this is accomplished by adjusting the scaling resistor RT.
Precise calibration of the AD654 requires the use of an accurate
voltage standard set to the desired FS value and an accurate
frequency meter. A scope is handy for monitoring output wave-
shape. Verification of converter linearity requires the use of a
switchable voltage source or DAC having a linearity error below
± 0.005%, and the use of long measurement intervals to mini-
mize count uncertainties. Since each AD654 is factory tested for
linearity, it is unnecessary for the end-user to perform this tedious
and time consuming test on a routine basis.
Sufficient FS calibration trim range must be provided to accom-
modate the worst-case sum of all major scaling errors. This
includes the AD654’s 10% full-scale error, the tolerance of the
fixed scaling resistor, and the tolerance of the timing capacitor.
Therefore, with a resistor tolerance of 1% and a capacitor tolerance
of 5%, the fixed part of the scaling resistor should be a maximum
of 84% of nominal, with the variable portion selected to allow
116% of the nominal.
If the input is in the form of a negative current source, the scaling
resistor is no longer required, eliminating the capability of trim-
ming FS frequency in this fashion. Since it is usually not practical
to smoothly vary the capacitance for trimming purposes, an
alternative scheme such as the one shown in Figure 4 is needed.
Designed for a FS of 1 mA, this circuit divides the input into two
R2
100⍀
R4
392⍀
R3
IS 1k⍀
R1
100⍀
AD654
1mA
FS
–V
IR
*
ROFF
100k⍀
f = IS
(20V) CT
؎0.6V
*OPTIONAL
OFFSET TRIM
Figure 4. Current Source FS Trim
and flowing into Pin 3; it constitutes the signal current IT to be
converted. The second path, through another 100 Ω resistor R2,
carries the same nominal current. Two equal valued resistors
offer the best overall stability, and should be either 1% discrete
film units, or a pair from a common array.
Since the 1 mA FS input current is divided into two 500 µA legs
(one to ground and one to Pin 3), the total input signal current
(IS) is divided by a factor of two in this network. To achieve the
same conversion scale factor, CT must be reduced by a factor of
two. This results in a transfer unique to this hookup:
f
=
IS
(20 V ) CT
For calibration purposes, resistors R3 and R4 are added to the
network, allowing a ± 15% trim of scale factor with the values
shown. By varying R4’s value the trim range can be modified to
accommodate wider tolerance components or perhaps the cali-
bration tolerance on a current output transducer such as the
AD592 temperature sensor. Although the values of R1–R4 shown
are valid for 1 mA FS signals only, they can be scaled upward
proportionately for lower FS currents. For instance, they should
be increased by a factor of ten for a FS current of 100 µA.
In addition to the offsets generated by the input amplifier’s bias
and offset currents, an offset voltage induced parasitic current
arises from the current fork input network. These effects are
minimized by using the bias current compensation resistor ROFF
and offset trim scheme shown in Figure 3e.
Although device warm-up drifts are small, it is good practice to
allow the devices operating environment to stabilize before trim,
REV. B
–5–
5 Page 
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
PIN 1
0.430 (10.92)
0.348 (8.84)
85
0.280 (7.11)
0.240 (6.10)
14
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.100 (2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
8-Lead SOIC (SO-8)
(Narrow Body)
0.1968 (5.00)
0.1890 (4.80)
8
0.1574 (4.00)
0.1497 (3.80) 1
5
0.2440 (6.20)
4 0.2284 (5.80)
PIN 1
0.0500 (1.27)
BSC
0.0196 (0.50)
0.0099 (0.25) x 45؇
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.0688 (1.75)
0.0532 (1.35)
8؇
0.0192 (0.49)
0.0098 (0.25) 0؇
0.0138 (0.35)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
AD654
REV. B
–11–
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet AD654.PDF ] | |
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