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AD6458 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD6458
Beschreibung GSM 3 V Receiver IF Subsystem
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
AD6458 Datasheet, Funktion
a
FEATURES
Fully Compliant with Standard and Enhanced GSM
Specification
–12 dBm Input 1 dB Compression Point
–2 dBm Input Third Order Intercept
10 dB SSB Noise Figure (330 )
DC–400 MHz RF and LO Bandwidths
Linear IF Amplifier
Linear-in-dB and Stable over Temperature Voltage
Gain Control
Quadrature Demodulator
Onboard Phase-Locked Quadrature Oscillator
Demodulates IFs from 5 MHz to 50 MHz
Low Power
9 mA at Midgain
1 A Sleep Mode Operation
3.0 V to 3.6 V Operation
Interfaces to AD7013, AD7015 and AD6421 Baseband
Converters
20-Lead SSOP
GSM 3 V Receiver IF Subsystem
AD6458
FUNCTIONAL BLOCK DIAGRAM
LO
RF
AGC
FREF
BPF
PLO
I
Q
AD6458
GENERAL DESCRIPTION
The AD6458 is a 3 V, low power receiver IF subsystem for
operation at input frequencies as high as 400 MHz and IFs from
5 MHz up to 50 MHz. It is optimized for operation in GSM,
DCS1800 and PCS1900 receivers. It consists of a mixer, IF
amplifier, I and Q demodulators, a phase-locked quadrature
oscillator, precise AGC subsystem, and a biasing system with
external power-down.
The low noise, high intercept mixer of the AD6458 is a
doubly-balanced Gilbert cell type. It has a nominal –12 dBm
input-referred 1 dB compression point and a –2 dBm input-
referred third-order intercept. The mixer section of the AD6458
also includes a local oscillator (LO) preamplifier, which lowers
the required LO drive to –16 dBm.
The gain control input accepts an external gain-control voltage
input from an external AGC detector or a DAC. It provides an
80 dB gain range with 27 mV/dB gain scaling.
The I and Q demodulators provide inphase and quadrature
baseband outputs to interface with Analog Devices’ AD7013
(IS54, TETRA, MSAT) and AD7015 and AD6421 (GSM,
DCS1800, PCS1900) baseband converters. An onboard
quadrature VCO which is externally phase-locked to the IF
signal drives the I and Q demodulators. This locked reference
signal is normally provided by an external VCTCXO under the
control of the radio’s digital processor. The AD6458 can also
provide demodulation of N-PSK and N-QAM in many non-
TDMA systems when used with external analog carrier recovery
systems such as the Costas Loop. Finally, the VCO can be
phase-locked to a frequency which is deliberately offset from the
IF, as in the case of a Beat-Frequency Oscillator (BFO), result-
ing in the product detection of CW or SSB.
The AD6458 uses supply voltages from 3.0 V to 3.6 V over the
temperature range of –40°C to +85°C. Operation is enabled by
a CMOS logical level; response time is typically <80 µs. When
disabled, the standby current is reduced to 1 µA.
The AD6458 comes in a 20-lead shrink small outline (SSOP)
surface-mount package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997






AD6458 Datasheet, Funktion
AD6458
22
20
18
16
14
FIF = 13MHz, ZS = 50
12
10
FIF = 26MHz, ZS = 50
8
FIF = 13MHz, ZS = 400
6
80 120 160 200 240 280 320 360 400 440
RF FREQUENCY – MHz
Figure 5. Mixer Noise Figure vs. RF Frequency
35
= 7.7dB
30 = 0.26dB
25
20
15
10
5
0
7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4
NOISE FIGURE – dB
Figure 6. Mixer Noise Figure Histogram, RS = 1 k,
FRF = 83 MHz, FIF = 13 MHz
2.0
1.6
RSH, VGAIN = 1.0V
CSH, VGAIN = 0.2V
5.5
5.0
1.2 4.5
RSH, VGAIN = 2.2V
CSH, VGAIN = 1.0V
0.8
0.4 RSH, VGAIN = 0.2V
CSH, VGAIN = 2.2V
4.0
3.5
0 3.0
50 100 150 200 250 300 350 400 450 500 550
RF FREQUENCY – MHz
Figure 7. Mixer Input Impedance vs. RF Frequency,
VPOS = 3.0 V, TA = +25°C
15
VGAIN = 0.2V
10
5
VGAIN = 1.2V
0
–5
VGAIN = 2.2V
–10
–15
50
100 150 200 250 300 350 400 450 500 550
RF FREQUENCY – MHz
Figure 8. Mixer Conversion Gain vs. RF Frequency,
TA = +25 °C, VPOS = 3.0 V, VREF =1.2 V, FIF =13 MHz
12
10
VGAIN = 0.2V
8
6
4
2
0 VGAIN = 1.5V
–2
–4
–6
VGAIN = 2.2V
–8
–10
10 14 18 22 26 30 34 38 42 46 50 54
IF FREQUENCY – MHz
Figure 9. Mixer Conversion Gain vs. IF Frequency,
TA = +25 °C, VPOS = 3 V, VREF = 1.2 V, FRF = 250 MHz
15
10
VPOS = 3V TO 3.6V
TA = –25°C TO +85°C
5
0
–5
–10
–15
0
0.5 1.0 1.5 2.0 2.5
VGAIN – Volts
Figure 10. Mixer Conversion Gain vs VGAIN, VREF = 1.2 V,
FIF =13 MHz, FRF = 83 MHz
–6– REV. 0

6 Page









AD6458 pdf, datenblatt
AD6458
I/Q Convention
The AD6458 is a complete IF receive subsystem. Although not
a requirement for using the AD6458, most applications will use
a high-side LO injection on pin LOIP (Pin 4) of the mixer. The
I and Q convention is such that when a spectrum with I leading
Q is presented to the input of the mixer, and a high-side LO is
presented on pin LOIP, I still leads Q at the baseband output of
the AD6458.
Phase-Locked Loop
The demodulators are driven by quadrature signals provided by
a variable frequency quadrature oscillator (VFQO), phase-
locked to a reference signal applied to Pin FREF. When this
signal is at the IF, in-phase and quadrature baseband outputs
are generated at the I output (IRXP and IRXN) and Q output
(QRXP and QRXN), respectively. The quadrature accuracy of
this VFQO is typically 2° at 13 MHz. A simplified diagram of
the FREF input is shown in Figure 35.
5k
VPOS
FREF
20k
5k
50µA PTAT
Figure 35. Simplified Schematic of the FREF Interface
The VFQO operates from 5 MHz to 50 MHz and is controlled
by the voltage between VPOS and FLTR. In normal operation, a
series RC network, forming the PLL loop filter, is connected
from FLTR to VPOS. The use of an integral sample-hold system
ensures that the frequency-control voltage on pin FLTR re-
mains held during power-down, so reacquisition of the carrier
occurs in less than 80 µs.
In practice, the probability of a phase mismatch at power-up is
high, so the worst-case linear settling period to full lock needs to
be considered in making filter choices. This is typically < 80 µs
for a quadrature phase error of ± 3° at an IF of 13 MHz. Note
that the VFQO always provides quadrature between its own I
and Q outputs, but the phasing between it and the reference
carrier will swing around the final value during the PLL’s set-
tling time.
Bias System
The AD6458 operates from a single supply, VPOS, usually 3.3 V,
at a typical supply current of 9 mA at midgain and TA = +25°C.
Any voltage from 3.0 V to 3.6 V may be used.
The bias system includes a fast acting active high CMOS-
compatible power-up switch, allowing the part to idle at 1 µA
when disabled. Biasing is generally proportional-to-absolute-
temperature (PTAT) to ensure stable gain with temperature.
Other special biasing techniques are used to ensure very accu-
rate gain, stable over the full temperature range.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Plastic SSOP
(RS-20)
0.295 (7.50)
0.271 (6.90)
20 11
1 10
0.078 (1.98) PIN 1
0.068 (1.73)
0.07 (1.78)
0.066 (1.67)
0.008 (0.203)
0.002 (0.050)
0.0256
(0.65)
BSC
8°
SEATING 0.009 (0.229) 0°
PLANE 0.005 (0.127)
0.037 (0.94)
0.022 (0.559)
–12–
REV. 0

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