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AD8019 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8019
Beschreibung DSL Line Driver with Power-Down
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD8019 Datasheet, Funktion
a
FEATURES
Low Distortion, High Output Current Amplifiers
Operate from 12 V to ؎12 V Power Supplies,
Ideal for High-Performance ADSL CPE, and xDSL
Modems
Low Power Operation
9 mA/Amp (Typ) Supply Current
Digital (1-Bit) Power-Down
Voltage Feedback Amplifiers
Low Distortion
Out-of-Band SFDR –80 dBc @ 100 kHz into 100 Line
High Speed
175 MHz Bandwidth (–3 dB), G = +1
400 V/s Slew Rate
High Dynamic Range
VOUT to within 1.2 V of Power Supply
APPLICATIONS
ADSL, VDSL, HDSL, and Proprietary xDSL USB, PCI,
PCMCIA Modems, and Customer Premise Equipment
(CPE)
PRODUCT DESCRIPTION
The AD8019 is a low cost xDSL line driver optimized to drive a
minimum of 13 dBm into a 100 load while delivering outstand-
ing distortion performance. The AD8019 is designed on a 24 V
high-speed bipolar process enabling the use of ± 12 V power
supplies or 12 V only. When operating from a single 12 V sup-
ply the highly efficient amplifier architecture can typically deliver
170 mA output current into low impedance loads through a
1:2 turns ratio transformer. Hybrid designs using ± 12 V supplies
enable the use of a 1:1 turns ratio transformer, minimizing attenu-
ation of the receive signal. The AD8019 typically draws 9 mA/
amplifier quiescent current. A 1-bit digital power down feature
reduces the quiescent current to approximately 1.6 mA/amplifier.
Figure 1 shows typical Out of Band SFDR performance under
ADSL CPE (upstream) conditions. SFDR is measured while
driving a 13 dBm ADSL DMT signal into a 100 line with
50 back termination.
The AD8019 comes in thermally enhanced 8-lead SOIC and
14-lead TSSOP packages. The 8-lead SOIC is pin-compatible
with the AD8017 12 V line driver.
DSL Line Driver
with Power-Down
AD8019
PIN CONFIGURATIONS
8-Lead SOIC
(R-8)
14-Lead TSSOP
(RU-14)
OUT1 1 AD8019AR 8 +VS
–IN1 2
7 OUT2
+IN1 3
6 –IN2
–VS 4
5 +IN2
NC 1
OUT1 2
–IN1 3
AD8019ARU 14 NC
13 +VS
12 OUT2
+IN1 4
11 –IN2
–VS 5
PWDN 6
10 +IN2
9 NC
NC 7
8 DGND
NC = NO CONNECT
80dBc
132.5
137.5
FREQUENCY kHz
142.5
Figure 1. Out-of-Band SFDR; VS = ±12 V; 13 dBm Output
Power into 200 , Upstream
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






AD8019 Datasheet, Funktion
AD8019
20
30
40
50
60
70
2ND
3RD
80
90
100
0.01
0.1
FREQUENCY MHz
1
5
TPC 7. Distortion vs. Frequency; VS = ±12 V, RL = 200 ,
Differential, VO = 16 V p-p
30
40
50
60
70 3RD HARMONIC
2ND HARMONIC
80
90
100
50
75 100 125 150 175
PEAK OUTPUT CURRENT mA
200
TPC 8. Distortion vs. Peak Output Current; VS = ±6 V;
RL = 10 ; f = 100 kHz; Single-Ended; Second Harmonic
20
30
40
50
60
2ND HARMONIC
70
3RD HARMONIC
80
90
100
50
75 100 125 150 175 200 225 250
PEAK OUTPUT CURRENT mA
TPC 9. Distortion vs. Peak Output Current; VS = ±12 V;
RL = 25 ; f = 100 kHz; Single-Ended; Second Harmonic
20
30
40
50
3RD
60
70
80
2ND
90
100
0.01
0.1
FREQUENCY MHz
1
5
TPC 10. Distortion vs. Frequency; VS = ±6 V, RL = 50 ,
Differential, VO = 3 V p-p
20
30
40
50
60
70
2ND
3RD
80
90
100
0
2 4 6 8 10 12 14 16 18
DIFFERENTIAL OUTPUT VOLTAGE V p-p
20
TPC 11. Distortion vs. Output Voltage; f = 100 kHz,
VS = ±6 V, G = +10, RL = 50 , Differential
10
20
30
40
50
2ND
60
70
80
90 3RD
100
110
0
2 4 6 8 10 12 14 16 18
DIFFERENTIAL OUTPUT VOLTAGE V p-p
20
TPC 12. Distortion vs. Output Voltage; f = 500 kHz,
VS = ±6 V, G = +10, RL = 50 , Differential
–6– REV. 0

6 Page









AD8019 pdf, datenblatt
AD8019
Table II. Junction Temperature vs. Line Power and Operating
Voltage for SOIC
PLINE, dBm
13
14
15
16
17
18
؎12
137
140
142
145
147
150
VSUPPLY
؎12.5
140
142
145
148
150
153
؎13
143
145
148
151
154
157
Table III. Junction Temperature vs. Line Power and
Operating Voltage for TSSOP
PLINE, dBm
13
14
15
16
VSUPPLY
+12 +13
115 118
116 119
118 121
120 123
Table IV. Junction Temperature vs. Line Power and
Operating Voltage for SOIC
PLINE, dBm
13
14
15
16
VSUPPLY
+12 +13
118 121
120 123
122 125
124 128
Thermal stitching, which connects the outer layers to the inter-
nal ground plane(s), can help to utilize the thermal mass of the
PCB to draw heat away from the line driver and other active
components.
LAYOUT CONSIDERATIONS
As is the case with all high-speed applications, careful attention
to printed circuit board layout details will prevent associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board
to provide a low-impedance return path. Removing the ground
plane on all layers from the areas near the input and output pins
will reduce stray capacitance, particularly in the area of the
inverting inputs. The signal routing should be short and direct
in order to minimize parasitic inductance and capacitance asso-
ciated with these traces. Termination resistors and loads should
be located as close as possible to their respective inputs and
outputs. Input and output traces should be kept as far apart as
possible to minimize coupling (crosstalk) though the board.
Wherever there are complementary signals, a symmetrical
layout should be provided to the extent possible to maximize
balanced performance. When running differential signals over a
long distance, the traces on the PCB should be close together or
any differential wiring should be twisted together to minimize
the area of the loop that is formed. This will reduce the radiated
energy and make the circuit less susceptible to RF interference.
Adherence to stripline design techniques for long signal traces
(greater than about 1 inch) is recommended.
Evaluation Board
The AD8019 is available installed on an evaluation board for
both package styles. Figures 8 and 9 show the schematics for the
TSSOP evaluation board.
The receiver circuit on these boards is typically unpopulated.
Requesting samples of the AD8022AR, along with either of the
AD8019 evaluation boards, will provide the capability to evaluate
the AD8019 along with other Analog Devices products in a typical
transceiver circuit. The evaluation circuits have been designed
to replicate the CPE side analog transceiver hybrid circuits.
The circuit mentioned above is designed using a 1-transformer
transceiver topology including a line receiver, line driver, line
matching network, an RJ11 jack for interfacing to line simula-
tors, and differential inputs.
AC-coupling capacitors of 0.1 µF, C8, and C10, in combination
with 10 k, resistors R24 and R25, will form a 1st order high-
pass pole at 160 Hz.
Transformer Selection
Customer premise ADSL requires the transmission of a 13 dBm
(20 mW) DMT signal. The DMT signal has a crest factor of 5.3,
requiring the line driver to provide peak line power of 560 mW.
560 mW peak line power translates into a 7.5 V peak voltage on
a 100 telephone line. Assuming that the maximum low distor-
tion output swing available from the AD8019 line driver on a
± 12 V supply is 20 V and taking into account the power lost due
to the termination resistance, a step-up transformer with turns
ratio of 1:1 is adequate for most applications. If the modem
designer desires to transmit more than 13 dBm down the twisted
pair, a higher turns ratio can be used for the transformer. This
trade-off comes at the expense of higher power dissipation by
the line driver as well as increased attenuation of the downstream
signal that is received by the transceiver.
In the simplified differential drive circuit shown in Figure 7,
the AD8019 is coupled to the phone line through a step-up
transformer with a 1:1 turns ratio. R1 and R2 are back termi-
nation or line matching resistors, each 50 (100 /(2 × 12))
where 100 is the approximate phone line impedance. A
transformer reflects impedance from the line side to the IC
side as a value inversely proportional to the square of the turns
ratio. The total differential load for the AD8019, including the
termination resistors, is 200 . Even under these conditions
the AD8019 provides low distortion signals to within 2 V of
the power supply rails.
One must take care to minimize any capacitance present at the
outputs of a line driver. The sources of such capacitance can
include, but are not limited to EMI suppression capacitors,
overvoltage protection devices and the transformers used in the
hybrid. Transformers have two kinds of parasitic capacitances,
distributed, or bulk capacitance, and interwinding capacitance.
Distributed capacitance is a result of the capacitance created
between each adjacent winding on a transformer. Interwinding
capacitance is the capacitance that exists between the windings
on the primary and secondary sides of the transformer. The
existence of these capacitances is unavoidable, but in specifying
–12–
REV. 0

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