|
|
PDF AD7899 Data sheet ( Hoja de datos )
| Número de pieza | AD7899 | |
| Descripción | 5V Single Supply 14-Bit 400 kSPS ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD7899 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
a
FEATURES
Fast (2.2 s) 14-Bit ADC
400 kSPS Throughput Rate
0.3 s Track/Hold Acquisition Time
Single Supply Operation
Selection of Input Ranges: ؎10 V, ؎5 V and ؎2.5 V
0 V to 2.5 V and 0 V to 5 V
High-Speed Parallel Interface which Also Allows
Interfacing to 3 V Processors
Low Power, 80 mW Typ
Power-Saving Mode, 20 W Typ
Overvoltage Protection on Analog Inputs
Power-Down Mode via STBY Pin
5 V Single Supply
14-Bit 400 kSPS ADC
AD7899
STBY
VINA
VINB
FUNCTIONAL BLOCK DIAGRAM
AVDD
VREF
VDRIVE
AD7899
6k⍀
+
–
2.5V
REFERENCE
TRACK/HOLD
SIGNAL
SCALING
14-BIT
ADC
OUTPUT
LATCH
BUSY/EOC
CONVERSION
CONTROL
LOGIC
INT/EXT
CLOCK
SELECT
INT
CLOCK
RD
DB13
DB0
CS
GENERAL DESCRIPTION
The AD7899 is a fast, low-power, 14-bit A/D converter that
operates from a single 5 V supply. The part contains a 2.2 µs
successive-approximation ADC, a track/hold amplifier, 2.5 V
reference, on-chip clock oscillator, signal conditioning circuitry,
and a high-speed parallel interface. The part accepts analog input
ranges of ± 10 V, ± 5 V, ± 2.5 V, 0 V to 2.5 V, and 0 V to 5 V.
Overvoltage protection on the analog input for the part allows
the input voltage to be exceeded without damaging the parts.
Speed of conversion can be controlled either by an internally
trimmed clock oscillator or by an external clock.
A conversion start signal (CONVST) places the track/hold into
hold mode and initiates conversion. The BUSY/EOC signal
indicates the end of the conversion.
Data is read from the part via a 14-bit parallel data bus using the
standard CS and RD signals. Maximum throughput for the
AD7899 is 400 kSPS.
The AD7899 is available in a 28-lead SOIC and SSOP packages.
CONVST
CLKIN
GND OPGND
PRODUCT HIGHLIGHTS
1. The AD7899 features a fast (2.2 µs) ADC allowing through-
put rates of up to 400 kSPS.
2. The AD7899 operates from a single 5 V supply and con-
sumes only 80 mW typ making it ideal for low power and
portable applications.
3. The part offers a high-speed parallel interface. The interface
can operate in 3 V and 5 V mode allowing for easy connec-
tion to 3 V or 5 V microprocessors, microcontrollers, and
digital signal processors.
4. The part is offered in three versions with different analog
input ranges. The AD7899-1 offers the standard industrial
ranges of ± 10 V and ± 5 V; the AD7899-2 offers a unipolar
range of 0 V to 2.5 or 0 V to 5 V, and the AD7899-3 has an
input range of ± 2.5 V.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
AD7899
TIMING CHARACTERISTICS1, 2 (VDD = 5 V ؎ 5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; All specifications TMIN
to TMAX and valid for VDRIVE = 3 V ؎ 5% and 5 V ؎ 5% unless otherwise noted.)
Parameter
A, B and S
Versions
Unit
Test Conditions/Comments
tCONV
tACQ
tEOC
tWAKE-UP – External VREF5
t1
t2
2.2
2.46
0.3
120
180
2
35
70
µs max
µs max
µs max
ns min
ns max
µs max
ns min
ns min
Conversion Time, Internal Clock
CLKIN = 6.5 MHz
Acquisition Time
EOC Pulsewidth
STBY Rising Edge to CONVST Rising Edge
(See Standby Mode Operation)
CONVST Pulsewidth
CONVST Rising Edge to BUSY Rising Edge
Read Operation
t3
t4
t5
t63
t74
t8
External Clock
t9
t10
t11
0
ns min
CS to RD Setup Time
0
ns min
CS to RD Hold Time
35
ns min
Read Pulsewidth
35
ns max
Data Access Time after Falling Edge of RD, VDRIVE = 5 V
40
ns max
Data Access Time after Falling Edge of RD, VDRIVE = 3 V
5
ns min
Bus Relinquish Time after Rising Edge of RD
30 ns max
0
ns min
BUSY Falling Edge to RD Delay
0
ns min
CLKIN to CONVST Rising Edge Setup Time
20
ns min
CLKIN to CONVST Rising Edge Hold Time
100
ns min
CONVST Rising Edge to CLK Falling Edge
NOTES
1 Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V DRIVE) and timed from a voltage level of VDRIVE/2.
2 See Figures 5, 6, 7, and 8.
3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
5 Refer to the Standby Mode Operation section.
Specifications subject to change without notice.
1.6mA
TO
OUTPUT
PIN
50pF
1.6V
400A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
–4– REV. A
5 Page 
AD7899
AD7899-3
Figure 4 shows the analog input section of the AD7899-3. The
analog input range is ± 2.5 V on the VINA input. The VINB input
can be left unconnected but if it is connected to a potential then
that potential must be GND.
6k⍀
VREF
VINA
R2
2.5V
REFERENCE
AD7899-3
TO ADC
REFERENCE
CIRCUITRY
R1
TO INTERNAL
COMPARATOR
TRACK/HOLD
VINB
Figure 4. AD7899-3 Analog Input Structure
For the AD7899-3, R1 = 4 kΩ and R2 = 4 kΩ. The resistor
input stage is followed by the high input impedance stage of the
track/hold amplifier.
The designed code transitions take place midway between suc-
cessive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs
etc.) LSB size is given by the formula, 1 LSB = FSR/16384.
Output coding is two’s complement binary with 1 LSB = FSR/
16384 = 5 V/16384 = 610.4 µV. The ideal input/output transfer
function for the AD7899-3 is shown in Table III.
Table III. Ideal Input/Output Code Table for the AD7899-3
Analog Inputl
+FSR/2 – 3/2 LSB2
+FSR/2 – 5/2 LSB
+FSR/2 – 7/2 LSB
Digital Output
Code Transition
011 . . . 110 to 011 . . . 111
011 . . . 101 to 011 . . . 110
011 . . . 100 to 011 . . . 101
GND + 3/2 LSB
GND + 1/2 LSB
GND – 1/2 LSB
GND – 3/2 LSB
000 . . . 001 to 000 . . . 010
000 . . . 000 to 000 . . . 001
111 . . . 111 to 000 . . . 000
111 . . . 110 to 111 . . . 111
–FSR/2 + 5/2 LSB
–FSR/2 + 3/2 LSB
–FSR/2 + 1/2 LSB
100 . . . 010 to 100 . . . 011
100 . . . 001 to 100 . . . 010
100 . . . 000 to 100 . . . 001
NOTES
1FSR is full-scale range is 5 V, with VREF = 2.5 V
21 LSB = FSR/16384 = 610.4 µV (± 2.5 V – AD7899-3) with VREF = 2.5 V.
TIMING AND CONTROL
Starting a Conversion
The conversion is initiated by applying a rising edge to the
CONVST signal. This places the track/hold into hold mode and
starts the conversion. The status of the conversion is indicated
by the dual function signal BUSY/EOC. The AD7899 can operate
in two conversion modes, EOC (End Of Conversion) mode and
BUSY mode. The operating mode is determined by the state of
CONVST at the end of the conversion.
Selecting a Conversion Clock
The AD7899 has an internal laser trimmed oscillator which can
be used to control the conversion process. Alternatively an external
clock source can be used to control the conversion process. The
highest external clock frequency allowed is 6.5 MHz. This means
a conversion time of 2.46 µs compared to 2.2 µs using the inter-
nal clock. However in some instances it may be useful to use an
external clock when high throughput rates are not required. For
example two or more AD7899s may be synchronized by using
the same external clock for all devices. In this way there is no
latency between output logic signals due to differences in the
frequency of the internal clock oscillators.
On the rising edge of CONVST the AD7899 will examine the
status of the CLKIN pin. If this pin is low it will use the internal
laser trimmed oscillator as the conversion clock. If the CLKIN pin
is high the AD7899 will wait for an external clock to be supplied
to this pin which will then be used as the conversion clock. The
first falling edge of the external clock should not happen for at
least 100 ns after the rising edge of CONVST to ensure correct
operation. Figure 5 shows how the BUSY/EOC output is synchro-
nized to the CLKIN signal. Each conversion requires 16 clocks.
The result of the conversion is transferred to the output data
register on the falling edge of the 15th clock cycle. When the
internal clock is selected the status of the CLKIN pin is free to
change during conversion but the CLKIN setup and hold times
must be observed in order to ensure that the correct conversion
clock is used. The CLKIN pin can also be tied low permanently if
the internal conversion clock is to be used.
CLKIN
CONVST
t9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
t 11
BUSY/EOC
RD
CS
Figure 5. Using an External Clock
–10–
REV. A
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD7899.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD7890 | 12-Bit Serial Data Acquisition System | Analog Devices |
| AD7891 | 12-Bit High Speed Data Acquisition System | Analog Devices |
| AD7892 | LC2MOS Single Supply/ 12-Bit 600 kSPS ADC | Analog Devices |
| AD7893 | LC2MOS 12-Bit/ Serial 6 us ADC in 8-Pin Package | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |