Datenblatt-pdf.com


AD7886 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7886
Beschreibung LC2MOS 12-Bit/ 750 kHz/1 MHz/ Sampling ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD7886 Datasheet, Funktion
a
LC2MOS
12-Bit, 750 kHz/1 MHz, Sampling ADC
AD7886
FEATURES
750 kHz/1 MHz Throughput Rate
1 s/750 ns Conversion Time
12-Bit No Missed Codes Over Temperature
67 dB SNR at 100 kHz Input Frequency
Low Power—250 mW typ
Fast Bus Access Time—57 ns max
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
GENERAL DESCRIPTION
The AD7886 is a 12-bit ADC with a sample-and-hold amplifier
offering high speed performance combined with low power dissi-
pation. The AD7886 is a triple pass flash ADC that uses 15
comparators in a 4-bit flash technique to achieve 12-bit accuracy
in 1 µs/750 ns conversion time. An on-chip clock oscillator pro-
vides the appropriate timing for each of the three conversion
stages, eliminating the need for any external clocks. Acquisition
time of the sample-and-hold amplifier gives a resulting through-
put rate of 750 kHz/1 MHz.*
The AD7886 operates from ± 5 V power supplies. Pin-strappable
inputs offer a choice of three analog input ranges: 0 V to 5 V,
0 V to 10 V or ± 5 V.
In addition to the traditional dc accuracy specifications such as
linearity, offset and full-scale errors, the AD7886 is also speci-
fied for dynamic performance parameters, including harmonic
distortion and signal-to-noise ratio.
The AD7886 has a high speed digital interface with three-state
data outputs. Conversion control is provided by a CONVST in-
put. Data access is controlled by CS and RD inputs, standard
microprocessor signals. The data access time of less than 57 ns
means that the AD7886 can interface directly to most modern
microprocessors, including DSP processors.
*Contact your local salesperson for further information on the 1 MHz
version.
FUNCTIONAL BLOCK DIAGRAM
VIN1
VIN2
+5REF
SUM
VREF
AGND
VDD
R3 R5
10k
R4
10k
R1
9k
3.5k
+
T/H
R2
6.3k
CLOCK
OSCILLATOR
AND TIMER
15
COMPARATORS
AND
4-BIT FLASH
LOGIC
4096
RESISTOR
DAC
SEGMENT SELECT
CS RD CONVST
CONTROL
TIMER
BUSY
4-BIT
LATCH
4-BIT
LATCH
4-BIT
LATCH
THREE
STATE
OUTPUTS
AD7886
DB11
DB0
VSS DGND
The AD7886 is fabricated in Analog Devices’ Linear Com-
patible CMOS process, a mixed technology process that
combines precision bipolar circuits with low power CMOS
logic.
The AD7886 is available in both a 28-pin DIP and a 28-pin
leaded chip carrier.
PRODUCT HIGHLIGHTS
1. Fast 1.33 µs/1 µs Throughput Time.
Fast throughput time makes the AD7886 suitable for a
wide range of data acquisition applications.
2. Dynamic Specifications for DSP Users.
The AD7886 is specified for ac parameters, including
signal-to-noise ratio, harmonic distortion and inter-
modulation distortion. Key digital timing parameters are
also tested and guaranteed over the full operating tem-
perature range.
3. Fast Microprocessor Interface.
Standard control signals, CS and RD, and fast bus ac-
cess times make the AD7886 easy to interface to micro-
processors.
4. Low Power.
LC2MOS fabrication process gives low power dissipa-
tion of 250 mW.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997






AD7886 Datasheet, Funktion
AD7886
this amplifier typically by 20 MHz which is much greater than
the Nyquist limit of the ADC; as a result, it can be used for
undersampling applications. The track-and-hold amplifier ac-
quires the input signal to 12-bit accuracy in less than 333 ns.
The overall throughput time is equal to the conversion time
plus the track/ hold amplifier acquisition time, which is 1.333 µs
for the AD7886.
The operation of the track/hold amplifier is essentially transpar-
ent to the user. The track-to-hold transition occurs at the start
of conversion on the falling edge of CONVST. The conversion
procedure does not start until the rising edge of CONVST. The
width of the CONVST pulse low time determines the track-to
hold settling time. The track/hold reverts back to the track
mode at the end of conversion when BUSY has returned high.
0 TO 5V ANALOG INPUT RANGE
3.5k
0 TO 5V
VIN1 10k
VIN2 10k
+ TO
COMPARATORS
0 TO 10V ANALOG INPUT RANGE
3.5k
0 TO 10V VIN1 10k
VIN2 10k
+ TO
COMPARATORS
±5V ANALOG INPUT RANGE
3.5k
±5V VIN1 10k
+5V VIN2 10k
+ TO
COMPARATORS
Figure 3. Analog Input Range Configurations
ANALOG INPUT RANGES
The AD7886 has three user selectable analog input ranges: 0 V
to 5 V, 0 V to 10 V and ± 5 V. Figure 3 shows how to configure
the two analog inputs (VIN1 and VIN2) for these ranges.
UNIPOLAR OPERATION
Figure 4 shows a typical unipolar circuit for the AD7886. The
ideal input/output characteristic is shown in Figure 5. The
designed code transitions occur on integer multiples of 1 LSB.
The output code is natural binary with 1 LSB = FS/4096. FS is
either +5 V or +10 V, depending on how the analog inputs are
configured.
AIN
0 TO 5V
OR
0 TO 10V
+ 5V
VIN1
VDD
VIN2**
+V AGND
+VIN
VOUT + 5V
AD586
GND
AD7886*
+ 5REF
SUM
AD707
+
– 3.5V
VREF
C1
10µF
C2
0.1µF
VSS
–5V
*ADDITIONAL PINS OMITTED FOR CLARITY
**0 TO 5V RANGE: CONNECT VIN2 TO VIN1
0 TO 10V RANGE: CONNECT VIN2 TO AGND
Figure 4. Unipolar Operation
OUTPUT
CODE
11...111
11...110
11...101
11...100
00...011
1LSB = FS
4096
00...010
00...001
00...000
123
VIN, INPUT VOLTAGE (LSBS)
FS
FS – 1LSB
Figure 5. Ideal Input/Output Transfer Characteristic for
Unipolar Operation
–6– REV. B

6 Page









AD7886 pdf, datenblatt
AD7886
A15
A0
MREQ
ADDRESS BUS
ADDR
ENCODE
EN
TIMER
CONVST
CS
RD RD
INT BUSY
Z-80
8085A
CLK
OE
Q3 D3
Q0 D0
74HC374
AD7886*
DB3
DB0
DB11
DB4
D7
DATA BUS
D0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7886–Z-80/8085A Interface
APPLICATION HINTS
Good printed circuit (PC) board layout is as important as the
circuit design itself in achieving high speed A/D performance.
The AD7886’s comparators are required to make bit decisions
on an LSB size of 1.22 mV. To achieve this, the designer has to
be conscious of noise in both the ADC itself and in the preced-
ing analog circuitry. Switching mode power supplies are not rec-
ommended as the switching spikes will feed through to the
comparator, causing noisy code transitions. Other causes of con-
cern are ground loops and digital feedthrough from micropro-
cessors. These are factors that influence any ADC, and a proper
PC board layout that minimizes these effects is essential for best
performance.
LAYOUT HINTS
Ensure that the layout for the printed circuit board has the digi-
tal and analog signal lines separated as much as possible. Take
care not to run any digital track alongside an analog signal track.
Guard (screen) the analog input with AGND.
Establish a single point analog ground (star ground) separate
from the logic system ground at the AD7886 AGND or as close
as possible to the AD7886. Connect all other grounds and the
AD7886 DGND to this single analog ground point. Do not
connect any other digital grounds to this analog ground point.
Because low impedance analog and digital power supply com-
mon returns are essential to low noise operation of the ADC,
make the foil width for these tracks as wide as possible. The use
of ground planes minimizes impedance paths and also guards
the analog circuitry from digital noise. The circuit layout of Fig-
ures 25 and 26 have both analog and digital ground planes that are
kept separated and only joined together at the AD7886 AGND.
NOISE
Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling. In
applications where this is not possible, use a shielded cable be-
tween the source and the ADC. Reduce the ground circuit im-
pedance as much as possible since any potential difference in
grounds between the signal source and the ADC appears as an
error voltage in series with the input signal.
DATA ACQUISITION BOARD
Figure 23 shows a typical data acquisition circuit designed for a
microprocessor environment. The corresponding PC board lay-
out and silkscreen are shown in Figures 24 to 26.
The analog input to the AD7886 is buffered with an AD845 op
amp. A component grid is provided near the analog input on the
PC board that may be used for an antialiasing filter or any other
conditioning circuitry. To facilitate this option, a link (labeled
LK4) is required on the analog input.
An AD586 voltage reference and an AD707 op amp provide the
appropriate reference biasing required by the AD7886. The
ADC’s data outputs are buffered with 74HC374 latches. These
provide data bus isolation and improve data access time. Data
access time is reduced to under 30 ns, allowing interfacing to
virtually any microprocessor, including the high speed DSP pro-
cessors. Data format can be either a complete parallel load for
16-bit processors or a two-byte load for 8-bit processors.
INTERFACE CONNECTIONS
There are two connectors labeled SKT3 and SKT4. SKT3 is a
96-contact (3-row) connector, which is directly compatible with
the ADSP-2100 evaluation board prototype expansion connec-
tor. The expansion connector on the ADSP-2100 board has
eight decoded chip enable outputs labeled ECE1 to ECE8.
ECE6 is used to select the AD7886 data acquisition board. To
avoid selecting on-board RAM sockets at the same time, LK6
on the ADSP-2100 board must be removed. In addition, the
ADSP-2100 expansion connector has four interrupts labeled
EIRQ0 to EIRQ3. The AD7886’s BUSY output connects to
EIRQ0. SKT3 pinout is shown in Figure 23.
Data format to the ADSP-2100 connector is left justified, i.e.,
DB11 of the conversion result is connected to DMD15 of the
connector. DMD3 to DMD0 are always zero.
SKT4 is a 22-way (2 row) pin-header connector. This connec-
tor contains all the signal contacts as SKT3 with the exception
of EDMACK and the 4 trailing zeros of the 16-bit data word.
Only the 12-bit conversion results go to SKT4. The pinout is
shown in Figure 22.
DB0 22
DB2 20
DB4 18
DB6 16
DB8 14
DB10 12
BUSY 10
CS 8
NC
VCC
DGND
6
4
2
21 DB1
19 DB3
17 DB5
15 DB7
13 DB9
11 DB11
9 OUT1
7 OUT2
5 RD
3 VCC
1 DGND
NC = NO CONNECT
Figure 22. SKT4 Pinout
–12–
REV. B

12 Page





SeitenGesamt 16 Seiten
PDF Download[ AD7886 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD7880LC2MOS Single +5 V Supply/ Low Power/ 12-Bit Sampling ADCAnalog Devices
Analog Devices
AD7883LC2MOS 12-Bit/ 3.3 V Sampling ADCAnalog Devices
Analog Devices
AD7884LC2MOS 16-Bit/ High Speed Sampling ADCsAnalog Devices
Analog Devices
AD7885LC2MOS 16-Bit/ High Speed Sampling ADCsAnalog Devices
Analog Devices
AD7886LC2MOS 12-Bit/ 750 kHz/1 MHz/ Sampling ADCAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche