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PDF AD7885 Data sheet ( Hoja de datos )
| Número de pieza | AD7885 | |
| Descripción | LC2MOS 16-Bit/ High Speed Sampling ADCs | |
| Fabricantes | Analog Devices | |
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a
LC2MOS
16-Bit, High Speed Sampling ADCs
AD7884/AD7885
FEATURES
Monolithic Construction
Fast Conversion: 5.3 s
High Throughput: 166 kSPS
Low Power: 250 mW
APPLICATIONS
Automatic Test Equipment
Medical Instrumentation
Industrial Control
Data Acquisition Systems
Robotics
GENERAL DESCRIPTION
The AD7884/AD7885 is a 16-bit monolithic analog-to-digital
converter with internal sample-and-hold and a conversion time
of 5.3 µs. The maximum throughput rate is 166 kSPS. It uses a
two pass flash architecture to achieve this speed. Two input
ranges are available: ± 5 V and ± 3 V. Conversion is initiated by
the CONVST signal. The result can be read into a microproces-
sor using the CS and RD inputs on the device. The AD7884 has
a 16-bit parallel reading structure while the AD7885 has a byte
reading structure. The conversion result is in 2s complement
code.
The AD7884/AD7885 has its own internal oscillator which con-
trols conversion. It runs from ± 5 V supplies and needs a VREF+
of +3 V.
The AD7884 is available in a 40-pin plastic DIP package and in
a 44-pin PLCC package.
The AD7885 is available in a 28-pin plastic DIP package and
the AD7885A is available in a 44-pin PLCC package.
FUNCTIONAL BLOCK DIAGRAMS
±3VIN F ±3VIN S
AGNDS AGNDF AVDD AVSS VDD VSS
±5VIN S
±5VIN F
R2
3kΩ
R1
5kΩ
R3 3kΩ
C1
SW1
A1
R4 4kΩ
R6 R5
2kΩ 4kΩ
SW2
9-BIT
ADC
V REF–
A2
SW3
16-BIT
ACCURATE
DAC
9
TIMER
R7
2kΩ
AD7884
9
LATCH
+ 16
ALU
9
OD
UR
TI
PV
UE
TR
S
16
DB15
DB0
CONTROL
CS
RD
R8
2kΩ
VREF+ F VREF+ S V INV VREF– GND CONVST BUSY
DGND
±3VIN
AGNDS AGNDF AVDD AVSS VDD VSS
±5VIN S
±5VIN F
R2
3kΩ
R1
5kΩ
R3 3kΩ
C1
SW1
A1
R4 4kΩ
R6 R5
2kΩ 4kΩ
SW2
9-BIT
ADC
VREF–
A2
SW3
16-BIT 9
ACCURATE
DAC
TIMER
R7
2kΩ
AD7885
9
LATCH
+ 16
ALU
9
OD
UR
TI
PV
UE
TR
S
8
DB7
DB0
CONTROL
CS
RD
HBEN
R8
2kΩ
VREF+ F VREF+ S VINV VREF– GND CONVST BUSY DGND
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD7884/AD7885
ABSOLUTE MAXIMUM RATINGS1
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to –7 V
AGND Pins to DGND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
AVDD to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVSS to VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
GND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VINS, VINF to AGND . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
VREF+ to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
VREF– to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
VINV to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C
Industrial Cerdip (A, B Versions) . . . . . . . . –40°C to +85°C
Extended Cerdip (T Versions) . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2If the AD7884/AD7885 is being powered from separate analog and digital supplies,
AVSS should always come up before VSS. See Figure 12 for a recommended
protection circuit using Schottky diodes.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
DIP PLCC
V INV 1
V REF– 2
±3V IN S 3
±3V IN F 4
±5V IN S 5
±5V IN F 6
AGNDS 7
AGNDF 8
AVDD 9
AVSS 10
GND 11
GND 12
VSS 13
VSS 14
AD7884
TOP VIEW
(Not to Scale)
40 VREF+S
39 VREF+F
38 DB15
V REF– 1
±3V IN 2
±5VIN S 3
37 DB14
±5VIN F 4
36 DB13 AGNDS 5
35 DB12
AGNDF 6
34 DB11
33 DB10
32 DB9
AV DD 7
AV SS 8
GND 9
31 DB8
30 DGND
29 VDD
28 DB7
VSS 10
VDD 11
CONVST 12
CS 13
27 DB6
RD 14
AD7885
TOP VIEW
(Not to Scale)
28 V INV
27 VREF+S
26 VREF+F
25 DB7
24 DB6
23 DB5
22 DB4
21 DGND
20 DB3
19 DB2
18 DB1
17 DB0
16 BUSY
15 HBEN
VDD 15
CONVST 16
26 DB5
25 DB4
CS 17
24 DB3
RD 18
23 DB2
VSS 19
22 DB1
BUSY 20
21 DB0
6 5 4 3 2 1 44 43 42 41 40
±5VINF 7
AGNDS 8
AGNDF 9
AVDD 10
AVSS 11
NC 12
GND 13
GND 14
VSS 15
VSS 16
VDD 17
AD7884
TOP VIEW
(Not to Scale)
39 DB12
38 DB11
37 DB10
36 DB9
35 DB8
34 NC
33 DGND
32 VDD
31 DB7
30 DB6
29 DB5
18 19 20 21 22 23 24 25 26 27 28
NC = NO CONNECT
6 5 4 3 2 1 44 43 42 41 40
±5VINF
AGNDS
7
8
AGNDF 9
AVDD 10
AVSS 11
NC 12
GND 13
GND 14
VSS 15
VSS 16
VDD 17
AD7885A
TOP VIEW
(Not to Scale)
39 DB7
38 DB6
37 NC
36 DB5
35 DB4
34 NC
33 DGND
32 VDD
31 DB3
30 DB2
29 DB1
18 19 20 21 22 23 24 25 26 27 28
NC = NO CONNECT
REV. C
–5–
5 Page 
AD7884/AD7885
If the noise in the converter is too high for an application, it can
be reduced by oversampling and digital filtering. This involves
sampling the input at higher than the required word rate and
then averaging to arrive at the final result. The very fast conver-
sion time of the AD7884/AD7885 makes it very suitable for
oversampling. For example, if the required input bandwidth is
40 kHz, the AD7884/AD7885 could be oversampled by a factor
of 2. This yields a 3 dB improvement in the effective SNR per-
formance. The noise performance in the ± 5 volt input range is
now effectively 85 µV rms and the resultant spread of codes for
2500 conversions will be four. This is shown in Figure 15.
1500
1000
500
16
15
14
13
12
11
10
0
20 40 60
FREQUENCY – kHz
80
Figure 17. Effective Number of Bits vs. Frequency
The effective number of bits for a device can be calculated from
its measured SNR. Figure 17 shows a typical plot of effective
number of bits versus frequency for the AD7884. The sampling
frequency is 166 kHz.
0
(X – 1) (X) (X + 1) (X + 2)
CODE
Figure 15. Histogram of 2500 Conversions of a DC Input
Using a ×2 Oversampling Ratio
Dynamic Performance
With a combined conversion and acquisition time of 6 µs, the
AD7884/AD7885 is ideal for wide bandwidth signal processing
applications. Signal to (Noise + Distortion), Total Harmonic
Distortion, Peak Harmonic or Spurious Noise and Intermodula-
tion Distortion are all specified. Figure 16 shows a typical
FFT plot of a 1.8 kHz, ± 5 V input after being digitized by the
AD7884/AD7885.
0
f IN = 1.8kHz, ± 5V SINE WAVE
fSAMPLE = 163kHz
–30 SNR = 87dB
THD = –95dB
–60
–90
–120
MICROPROCESSOR INTERFACING
The AD7884/AD7885 is designed on a high speed process
which results in very fast interfacing timing (Data Access Time
of 57 ns max). The AD7884 has a full 16-bit parallel bus, and
the AD7885 has an 8-bit wide bus. The AD7884, with its paral-
lel interface, is suited to 16-bit parallel machines whereas the
AD7885, with its byte interface, is suited to 8-bit machines.
Some examples of typical interface configurations follow.
AD7884 to MC68000 Interface
Figure 18 shows a general interface diagram for the MC68000,
16-bit microprocessor to the AD7884. In Figure 18, conversion
is initiated by bringing CSA low (i.e., writing to the appropriate
address). This allows the processor to maintain control over the
complete conversion process. In some cases it may be more
desirable to control conversion independent from the processor.
This can be done by using an external sampling timer.
A23 – A1
ADDRESS BUS
MC68000
DTACK
AS
R/W
D15 – D0
ADDRESS
DECODE LOGIC
CSB CSA
DATA BUS
AD7884
CONVST
CS
RD
DB15 – DB0
–150
2048 POINT FFT
Figure 16. AD7884/AD7885 FFT Plot
Effective Number of Bits
The formula for SNR (see Terminology section) is related to
the resolution or number of bits in the converter. Rewriting the
formula, below, gives a measure of performance expressed in
effective number of bits (N).
N = (SNR – 1.76)/6.02
Figure 18. AD7884 to MC68000 Interface
Once conversion has been started, the processor must wait until
it is completed before reading the result. There are two ways of
ensuring this. The first way is to simply use a software delay to
wait for 6.5 µs before bringing CS and RD low to read the data.
REV. C
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7885.PDF ] | |
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