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AD7878 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7878
Beschreibung LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP Interface
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD7878 Datasheet, Funktion
a LC2MOS Complete 12-Bit
100 kHz Sampling ADC with DSP Interface
AD7878
FEATURES
Complete ADC with DSP Interface, Comprising:
Track/Hold Amplifier with 2 s Acquisition Time
7 s A/D Converter
3 V Zener Reference
8-Word FIFO and Interface Logic
72 dB SNR at 10 kHz Input Frequency
Interfaces to High Speed DSP Processors, e.g.,
ADSP-2100, TMS32010, TMS32020
41 ns max Data Access Time
Low Power, 60 mW typ
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7878 is a fast, complete, 12-bit A/D converter with a
versatile DSP interface consisting of an 8-word, first-in, first-out
(FIFO) memory and associated control logic.
The FIFO memory allows up to eight samples to be digitized
before the microprocessor is required to service the A/D con-
verter. The eight words can then be read out of the FIFO at
maximum microprocessor speed. A fast data access time of
41 ns allows direct interfacing to DSP processors and high
speed 16-bit microprocessors.
An on-chip status/control register allows the user to program the
effective length of the FIFO and contains the FIFO out of
range, FIFO empty and FIFO word count information.
The analog input of the AD7878 has a bipolar range of ± 3 V.
The AD7878 can convert full power signals up to 50 kHz and is
fully specified for dynamic parameters such as signal-to-noise
ratio and harmonic distortion.
The AD7878 is fabricated in Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
The part is available in four package styles, 28-pin plastic and
hermetic dual-in-line package (DIP), leadless ceramic chip
carrier (LCCC) or plastic leaded chip carrier (PLCC).
PRODUCT HIGHLIGHTS
1. Complete A/D Function with DSP Interface
The AD7878 provides the complete function for digitizing
ac signals to 12-bit accuracy. The part features an on-chip
track/hold, on-chip reference and 12-bit A/D converter. The
additional feature of an 8-word FIFO reduces the high soft-
ware overheads associated with servicing interrupts in DSP
processors.
2. Dynamic Specifications for DSP Users
The AD7878 is fully specified and tested for ac parameters,
including signal-to-noise ratio, harmonic distortion and
intermodulation distortion. Key digital timing parameters
are also tested and specified over the full operating tempera-
ture range.
3. Fast Microprocessor Interface
Data access time of 41 ns is the fastest ever achieved in a
monolithic A/D converter, and makes the AD7878 compat-
ible with all modern 16-bit microprocessors and digital
signal processors.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997






AD7878 Datasheet, Funktion
AD7878
INTERNAL FIFO MEMORY
The internal FIFO memory of the AD7878 consists of eight
memory locations. Each word in memory contains 13 bits of
information—12 bits of data from the conversion result and one
additional bit which contains information as to whether the 12-
bit result is out of range or not. A block diagram of the AD7878
FIFO architecture is shown in Figure 3.
Figure 3. Internal FIFO Architecture
The conversion result is gathered in the successive approxima-
tion register (SAR) during conversion. At the end of conversion
this result is transferred to the FIFO memory. The FIFO ad-
dress pointer always points to the top of memory, which is the
uppermost location containing valid data. The pointer is incre-
mented after each conversion. A read operation from the FIFO
memory accesses data from the bottom of the FIFO, Location 0.
On completion of the read operation, each data word moves
down one location and the address pointer is decremented by
one. Therefore, each conversion result from the SAR enters at
the top of memory, propagates down with successive reads until
it reaches Location 0 from where it can be accessed by a micro-
processor read operation.
The transfer of information from the SAR to the FIFO occurs in
synchronization with the AD7878 input clock (CLK IN). The
propagation of data words down the FIFO is also synchronous
with this clock. As a result, a read operation to obtain data from
the FIFO must also be synchronous with CLK IN to avoid
Read/Write conflicts in the FIFO (i.e., reading from FIFO Loca-
tion 0 while it is being updated). This requires that the micro-
processor clock and the AD7878 CLK IN are derived from the
same source.
INTERNAL COMPARATOR TIMING
The ADC clock, which is applied to CLK IN, controls the suc-
cessive approximation A/D conversion process. This clock is
internally divided by four to yield a bit trial cycle time of 500 ns
min (CLK IN = 8 MHz clock). Each bit decision occurs 25 ns
after the rising edge of this divided clock. The bit decision is
latched by the rising edge of an internal comparator strobe sig-
nal. There are 12-bit decisions, as in a normal successive ap-
proximation routine, and one extra decision that checks if the
input sample is out of range. In a normal successive approxima-
tion A/D converter, reading data from the device during conver-
sion can upset the conversion in progress. This is due to on-chip
transients, generated by charging or discharging the databus,
concurrent with a bit decision. The scheme outlined below and
shown in Figure 4 describes how the AD7878 overcomes this
problem.
The internal comparator strobe on the AD7878 is gated with
both DMRD and DMWR so that if a read or write operation
occurs when a bit decision is about to be made, the bit decision
point is deferred by one CLK IN cycle. In other words, if
DMRD or DMWR goes low (with CS low) at any time during
the CLK IN low time immediately prior to the comparator
strobing edge (tLOW of Figure 4), the bit trial is suspended for a
clock cycle. This makes sure that the bit decision is latched at a
time when the AD7878 is not attempting to charge or discharge
the data bus, thereby ensuring that no spurious transients occur
internally near a bit decision point.
The decision point slippage mechanism is shown in Figure 4 for
the MSB decision. Normally, the MSB decision occurs 25 ns
after the fourth rising CLK IN edge after CONVST goes high.
However, in the timing diagram of Figure 4, CS and DMRD or
DMWR are low in the time period tLOW prior to the MSB deci-
sion point on the fourth rising edge. This causes the internal
comparator strobe to be slipped to the fifth rising clock edge.
The AD7878 will again check during a period tLOW prior to this
fifth rising clock edge; and if the CS and DMRD or DMWR are
still low, the bit decision point will be slipped a further clock
cycle.
The conversion time for the ADC normally consists of the 13-
bit trials described above and one extra internal clock cycle during
which data is written from the SAR to the FIFO. For an 8 MHz
input clock this results in a conversion time of 7 µs. However,
the software routine servicing the AD7878 has the potential to
read 16 times from the device during conversion—8 reads from
the FIFO and 8 reads from the status/control register. It also has
the potential to write once to the status/control register. If these
Figure 4. Operational Timing Diagram
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AD7878 pdf, datenblatt
AD7878
The MC68000 AS and R/W outputs are used to generate sepa-
rate DMWR and DMRD inputs for the AD7878. As with the
three interfaces previously described, WAIT states are inserted if
a read/write operation is attempted while the track/hold amplifier
is going from the track to the hold mode.
THROUGHPUT RATE
The AD7878 has a maximum specified throughput rate (sample
rate) of 100 kHz. This is a worst-case test condition and specifi-
cations apply for reduced sampling rates, provided that Nyquist
criterion is obeyed. The throughput rate must take into account
ADC CONVST pulse width, ADC conversion time and the
track/hold amplifier acquisition time. The time required for each
of these tasks is shown in Table II for a selection of DSP proces-
sors. Since the ADC clock has to be synchronized to the micro-
processor dock, the conversion time depends on the micro-
processor used. In addition, time must be allowed for reading data
from the AD7878. If this task is performed during the track/
hold amplifier acquisition period, then it does not impact the
overall throughput rate. However, if the read operations occur
during a conversion, they may stretch the conversion time and
reduce the track/hold amplifier acquisition time. The track/hold
amplifier requires a minimum of 2 µs to operate to specification.
The time required to read from the AD7878 depends on the
number of FIFO memory locations to be read and the software
organization.
As an example, consider an application using the ADSP-2100
and the AD7878 with a throughput rate of 100 kHz. The time
required for the CONVST pulse and the ADC conversion is
7.375 µs. This leaves 2.625 µs for the track/hold acquisition
time and for reading the ADC (both operations occurring in
parallel). The ADSP-2100, when operating from a 32 MHz
clock, has an instruction cycle of 125 ns and an interrupt re-
sponse time of 500 ns. This allows adequate time to perform
16 read operations within the time budget allowed.
Table II. AD7878 Throughput Rate
CONVST Conversion T/H Acquisition
Pulse Width Time
Time
Figure 21. AD7878–MC68000 Interface
Typical AD7878 Microprocessor Operating Sequence
After power-up or reset, the status/control register is initialized
by writing to the AD7878. This enables the ALFL output if
required for a microprocessor interrupt and sets the effective word
length of the FIFO memory. The processor now executes the
main body of the program while waiting for an ADC interrupt.
This interrupt will occur when the preprogrammed number of
samples are collected in the FIFO memory. The interrupt ser-
vice routine first interrogates DB5(FOOR) of the status/control
register to determine if any sample in the FIFO memory is out
of range. If all data samples are valid, then the program pro-
ceeds to read the FIFO memory. If, on the other hand, at least
one sample is out of range, then an overrange routine is called.
There are many actions that can be taken by the out of range
routine, the selection of which is application dependent. One
option is to ignore all the current samples residing in the FIFO
memory, reinitialize the status/control register and return to the
main body of the program. Another option is to check the indi-
vidual out of range status of each word in the FIFO memory
and to discard the invalid ones. The underrange or overrange
status of each word can also be determined and the analog input
adjusted accordingly before returning to the main program.
Note: there is no need to check the out-of-range status if the
analog input is always assured to be within range.
Number of
Clock Cycles
ADSP-21001
TMS320102
TMS320202
2 min
250 ns min
400 ns min
400 ns min
Non-
57 max
Applicable
7.125 µs max 2 µs min
11.14 µs max 2 µs min
11.14 µs max 2 µs min
NOTES
1ADSP-2100 Clock Frequency = 32 MHz.
2TMS320XX Clock Frequency = 20 MHz.
APPLICATION HINTS
Good printed circuit board (PCB) layout is as important as the
overall circuit design itself in achieving high speed A/D perfor-
mance. The AD7878 is required to make bit decisions on an
LSB size of 1.465 mV. To achieve this, the designer has to be
conscious of noise both in the ADC itself and in the preceding
analog circuitry. Switching mode power supplies are not recom-
mended as the switching spikes will feed through to the com-
parator, causing noisy code transitions. Other concerns are
ground loops and digital feedthrough from microprocessors.
These factors influence any ADC, and a proper PCB layout that
minimizes these effects is essential for best performance.
LAYOUT HINTS
Ensure that the layout for the printed circuit board has the
digital and analog signal lines separated as much as possible.
Take care not to run any digital track alongside an analog signal
track. Guard (screen) the analog input with AGND.
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