PDF AD7868 Data sheet ( Hoja de datos )

Número de pieza	AD7868
Descripción	LC2MOS Complete/ 12-Bit Analog I/O System
Fabricantes	Analog Devices
Logotipo
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No Preview Available ! a LC2MOS Complete, 12-Bit Analog I/O System AD7868 FEATURES Complete 12-Bit I/O System, Comprising: 12-Bit ADC with Track/Hold Amplifier 83 kHz Throughout Rate 72 dB SNR 12-Bit DAC with Output Amplifier 3 ␮s Settling Time 72 dB SNR On-Chip Voltage Reference Operates from ؎5 V Supplies Low Power – 130 mW typ Small 0.3" Wide DIP APPLICATIONS Digital Signal Processing Speech Recognition and Synthesis Spectrum Analysis High Speed Modems DSP Servo Control GENERAL DESCRIPTION The AD7868 is a complete 12-bit I/O system containing a DAC and an ADC . The ADC is a successive approximation type with a track-and-hold amplifier having a combined throughput rate of 83 kHz. The DAC has an output buffer amplifier with a settling time of 3 µs to 12 bits. Temperature compensated 3 V buried Zener references provide precision references for the DAC and ADC. Interfacing to both the DAC and ADC is serial, minimizing pin count and giving a small 24-pin package size. Standard control signals allow serial interfacing to most DSP machines. Asyn- chronous ADC conversion control and DAC updating is made possible with the CONVST and LDAC logic inputs. The AD7868 operates from ± 5 V power supplies, the analog in- put/output range of the ADC/DAC is ± 3 V. The part is fully specified for dynamic parameters such as signal-to-noise ratio and harmonic distortion as well as traditional dc specifications. The part is available in a 24-pin, 0.3" wide, plastic or hermetic dual-in-line package (DIP) and in a 28-pin, plastic SOIC package. FUNCTIONAL BLOCK DIAGRAM VDD RR RI DAC LDAC TFS TCLK DT CONTROL RFS RCLK DR CLK CONVST CLOCK AD7868 DGND 12-BIT DAC DAC SERIAL INTERFACE ADC SERIAL INTERFACE 12-BIT ADC DAC 3V REFERENCE ADC 3V REFERENCE R R TRACK/HOLD VSS AGND VOUT RO DAC RO ADC VIN PRODUCT HIGHLIGHTS 1. Complete 12-Bit I/O System. The AD7868 contains a 12-bit ADC with a track-and-hold amplifier and a 12-bit DAC with output amplifier. Also included are separate on-chip voltage references for the DAC and the ADC. 2. Dynamic Specifications for DSP Users. In addition to traditional dc specifications, the AD7868 is specified for ac parameters including signal-to-noise ratio and harmonic distortion. These parameters along with im- portant timing parameters are tested on every device. 3. Small Package. The AD7868 is available in a 24-pin DIP and a 28-pin SOIC package. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 1 page AD7868 PIN FUNCTION DESCRIPTION DIP Pin Number Mnemonic Function POWER SUPPLY 7 & 23 VDD 10 & 22 8 & 19 VSS AGND 6 &17 DGND Positive Power Supply, 5 V ± 5%. Both VDD pins must be tied together. Negative Power Supply, –5 V ± 5%. Both VSS pins must be tied together. Analog Ground. Both AGND pins must be tied together. Digital Ground. Both DGND pins must be tied together. ANALOG SIGNAL AND REFERENCE 21 VIN ADC Analog Input. The ADC input range is ± 3 V. 9 VOUT Analog Output Voltage from DAC. This output comes from a buffer amplifier. The range is bipolar, ± 3 V with RI DAC = +3 V. 20 RO ADC Voltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be used as a reference for the DAC by connecting it to the RI DAC input. The external load capability of this reference is 500 µA. 11 RO DAC DAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC with this internal reference, RO DAC should be connected to RI DAC. The external load capability of the reference is 500 µA. 12 RI DAC DAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is internally buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7868 is 3 V. ADC INTERFACE AND CONTROL 2 CLK Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying pin to VSS enables the internal laser-trimmed oscillator. 3 RFS Receive Frame Synchronization, Logic Output. This is an active low open-drain output which provides a framing pulse for serial data. An external 4.7 kΩ pull-up resistor is required on RFS. 4 RCLK Receive Clock, Logic Output. RCLK is the gated serial clock output which is derived from the internal or external ADC clock. If the CONTROL input is at VSS the clock runs continuously. With the CONTROL input at DGND the RCLK output is gated off (three-stated) after serial transmission is complete. RCLK is an open-drain output and requires an external 2 kΩ pull-up resistor. 5 DR Receive Data, Logic Output. This is an open-drain data output used in conjunction with RFS and RCLK to transmit data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is low. An external 4.7 kΩ resistor is required on the DR output. 1 CONVST Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into the hold mode and starts an ADC conversion. This input in asynchronous to the CLK input. 24 CONTROL Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the RCLK is continuous. Note, tying this pin to VDD places the part in a factory test mode where normal operation is not exhibited. DAC INTERFACE AND CONTROL 14 TFS Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC with serial data expected after the falling edge of this signal. 15 DT Transmit Data, Logic Input. This is the data input which is used in conjunction with TFS and TCLK to transfer serial data to the input latch. 16 TCLK Transmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when TFS is low. 13 LDAC Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the falling edge of this signal. 18 NC No Connect. REV. B –5– 5 Page AD7868 MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD7868 is via a serial bus that uses standard protocol compatible with DSP machines. The communication interface consists of separate transmit (DAC) and receive (ADC) sections whose operations can be either syn- chronous or asynchronous with respect to each other. Each sec- tion has a clock signal, a data signal and a frame or strobe pulse. Synchronous operation means that data is transmitted from the ADC and to the DAC at the same time. In this mode only one interface clock is needed and this has to be the ADC clock out, so RCLK must be connected to TCLK. For asynchronous op- eration, DAC and ADC data transfers are independent of each other, the ADC provides the receive clock (RCLK) while the transmit clock (TCLK) may be provided by the processor or the ADC or some other external clock source. Another option to be considered with serial interfacing is the use of a gated clock. A gated clock means that the device that is sending the data switches on the clock when data is ready to be transmitted and three states the clock output when transmission is complete. Only 16 clock pulses are transmitted with the first data bit getting latched into the receiving device on the first fall- ing clock edge. Ideally, there is no need for frame pulses, how- ever, the AD7868 DAC frame input (TFS) has to be driven high between data transmissions. The easiest method is to use RFS to drive TFS and use only synchronous interfacing. This avoids the use of interconnects between the processor and AD7868 frame signals. Not all processors have a gated clock facility, Figure 16 shows an example with the DSP56000. Table I below shows the number of interconnect lines between the processor and the AD7868 for the different interfacing op- tions. The AD7868 has the facility to use different clocks for transmitting and receiving data. This option, however, only ex- ists on some processors and normally just one clock (ADC clock) is used for all communication with the AD7868. For sim- plicity, all the interface examples in this data sheet use synchro- nous interfacing and use the ADC clock (RCLK) as an input for the DAC clock (TCLK). For a better understanding of each of these interfaces, consult the relevant processor data sheet. Table I. Interconnect Lines for Different Interfacing Options No. of Configuration Interconnects Signals Synchronous 4 Asynchronous* 5 or 6 Synchronous Gated Clock 3 RCLK, DR, DT and RFS (TCLK = RCLK, TFS = RFS) RCLK, DR, RFS, DT, TFS (TCLK = RCLK or µP serial CLK) RCLK, DR and DT (TCLK = RCLK, TFS = RFS) 5 LINES OF INTERCONNECT WHEN TCLK = RCLK 6 LINES OF INTERCONNECT WHEN TCLK = µP SERIAL CLK AD7868—DSP56000 Interface Figure 16 shows a typical interface between the AD7868 and DSP56000. The interface arrangement is synchronous with a gated clock requiring only three lines of interconnect. The DSP56000 internal serial control registers have to be configured for a 16-bit data word with valid data on the first falling clock edge. Conversion starts and DAC updating are controlled by an external timer. Data transfers, which occur during ADC conver- sions, are between the processor receive and transmit shift regis- ters and the AD7868’s ADC and DAC. At the end of each 16-bit transfer the DSP56000 receives an internal interrupt indi- cating the transmit register is empty and the receive register is full. TIMER CONVST LDAC CONTROL DSP56000 SC0 SCK SRD STD + 5V 4.7kΩ 2kΩ 4.7kΩ AD7868 RFS TFS RCLK DR DT TCLK ADDITIONAL PINS OMITTED FOR CLARITY Figure 16. AD7868—DSP56000 Interface AD7868—ADSP-2101/ADSP-2102 Interface An interface which is suitable for the ADSP-2101 or the ADSP- 2102 is shown in Figure 17. The interface is configured for syn- chronous, continuous clock operation. The LDAC is tied low so the DAC gets updated on the sixteenth falling clock after TFS goes low. Alternatively LDAC may be driven from a timer as shown in Figure 16. As with the previous interface the processor receives an interrupt after reading or writing to the AD7868 and updates its own internal registers in preparation for the next data transfer. TIMER CONVST ADSP-2101/ ADSP-2102 RFS SCLK DR TFS DT + 5V 4.7kΩ CONTROL – 5V AD7868 2kΩ 4.7kΩ RFS RCLK DR TFS TCLK DT *ADDITIONAL PINS OMITTED FOR CLARITY LDAC Figure 17. AD7868—ADSP-2101/ADSP-2102 Interface REV. B –11– 11 Page

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