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AD7859 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7859
Beschreibung 3 V to 5 V Single Supply/ 200 kSPS 8-Channel/ 12-Bit Sampling ADCs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD7859 Datasheet, Funktion
a
3 V to 5 V Single Supply, 200 kSPS
8-Channel, 12-Bit Sampling ADCs
AD7859/AD7859L*
FEATURES
Specified for VDD of 3 V to 5.5 V
AD7859–200 kSPS; AD7859L–100 kSPS
System and Self-Calibration
Low Power
Normal Operation
AD7859: 15 mW (VDD = 3 V)
AD7859L: 5.5 mW (VDD = 3 V)
Using Automatic Power-Down After Conversion (25 W)
AD7859: 1.3 mW (VDD = 3 V 10 kSPS)
AD7859L: 650 W (VDD = 3 V 10 kSPS)
Flexible Parallel Interface:
16-Bit Parallel/8-Bit Parallel
44-Pin PQFP and PLCC Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
GENERAL DESCRIPTION
The AD7859/AD7859L are high speed, low power, 8-channel,
12-bit ADCs which operate from a single 3 V or 5 V power
supply, the AD7859 being optimized for speed and the
AD7859L for low power. The ADC contains self-calibration
and system calibration options to ensure accurate operation over
time and temperature and have a number of power-down
options for low power applications.
The AD7859 is capable of 200 kHz throughput rate while the
AD7859L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7859 and AD7859L input
voltage range is 0 to VREF (unipolar) and –VREF/2 to +VREF/2
about VREF/2 (bipolar) with both straight binary and 2s comple-
ment output coding respectively. Input signal range is to the
supply and the part is capable of converting full-power signals to
100 kHz.
CMOS construction ensures low power dissipation of typically
5.4 mW for normal operation and 3.6 µW in power-down mode.
The part is available in 44-pin, plastic quad flatpack package
(PQFP) and plastic lead chip carrier (PLCC).
AIN1
AIN8
REFIN/
REFOUT
CREF1
CREF2
CAL
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
AD7859/AD7859L
I/P
MUX
T/H
2.5V
REFERENCE
BUF
COMP
CHARGE
REDISTRIBUTION
DAC
CALIBRATION MEMORY
AND
CONTROLLER
SAR + ADC
CONTROL
PARALLEL INTERFACE/CONTROL REGISTER
DB15 – DB0
RD CS WR W/B
DVDD
DGND
CLKIN
CONVST
BUSY
SLEEP
PRODUCT HIGHLIGHTS
1. Operation with either 3 V or 5 V power supplies.
2. Flexible power management options including automatic
power-down after conversion.
3. By using the power management options a superior power
performance at slower throughput rates can be achieved.
AD7859: 1 mW typ @ 10 kSPS
AD7859L: 1 mW typ @ 20 kSPS
4. Operates with reference voltages from 1.2 V to the supply.
5. Analog input ranges from 0 V to VDD.
6. Self and system calibration.
7. Versatile parallel I/O port.
8. Lower power version AD7859L.
*Patent pending.
See page 28 for data sheet index.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD7859 Datasheet, Funktion
AD7859/AD7859L
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Unipolar Offset Error
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in the unipolar mode.
Positive Full-Scale Error
This applies to the unipolar and bipolar modes and is the devia-
tion of the last code transition from the ideal AIN(+) voltage
(AIN(–) + Full Scale – 1.5 LSB) after the offset error has been
adjusted out.
Negative Full-Scale Error
This applies to the bipolar mode only and is the deviation of the
first code transition (10 . . . 000 to 10 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – VREF/2 + 0.5 LSB).
Bipolar Zero Error
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ± 1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N +1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7859/AD7859L, it is
defined as:
THD (dB) = 20 log
(V
2
2
+V
2
3
+V
2
4
+V
2
5
+V
2
6
)
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre-
quency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
–6– REV. A

6 Page









AD7859 pdf, datenblatt
AD7859/AD7859L
CALIBRATION REGISTERS
The AD7859/AD7859L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read
from all 10 calibration registers. In self and system calibration, the part automatically modifies the calibration registers; only if the
user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-
dressed (See Table V). The addressing applies to both the read and write operations for the calibration registers. The user should not
attempt to read from and write to the calibration registers at the same time.
CALSLT1 CALSLT0
00
01
10
11
Table V. Calibration Register Addressing
Comment
This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.
This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.
This combination addresses the Offset Register. One register in total.
This combination addresses the Gain Register. One register in total.
Writing to/Reading from the Calibration Registers
When writing to the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits.
When reading from the calibration registers a write to the con-
trol register is required to set the CALSLT0 and CALSLT1 bits
and also to set the RDSLT1 and RDSLT0 bits to 10 (this ad-
dresses the calibration registers for reading). The calibration
register pointer is reset on writing to the control register setting
the CALSLT1 and CALSLT0 bits, or upon completion of all
the calibration register write/read operations. When reset it
points to the first calibration register in the selected write/read
sequence. The calibration register pointer points to the gain
calibration register upon reset in all but one case, this case being
where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-
bration register is being accessed, the calibration register pointer
is automatically incremented after each full calibration register
write/read operation. The calibration register address pointer is
incremented after the high byte read or write operation in byte
mode. Therefore when reading (in byte mode) from the calibra-
tion registers, the low byte must always be read first, i.e., HBEN
= logic zero. The order in which the 10 calibration registers are
arranged is shown in Figure 5. Read/Write operations may be
aborted at any time before all the calibration registers have been
accessed, and the next control register write operation resets the
calibration register pointer. The flowchart in Figure 6 shows the
sequence for writing to the calibration registers. Figure 7 shows
the sequence for reading from the calibration registers.
CAL REGISTER
ADDRESS POINTER
CALIBRATION REGISTERS
GAIN REGISTER
OFFSET REGISTER
DAC 1st MSB REGISTER
(1)
(2)
(3)
When reading from the calibration registers there is always two
leading zeros for each of the registers.
START
WRITE TO CONTROL REGISTER SETTING STCAL = 0
AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
WRITE TO CAL REGISTER
(ADDR1 = 1, ADDR0 = 0)
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
?
YES
FINISHED
NO
Figure 6. Flowchart for Writing to the Calibration Registers
DAC 8th MSB REGISTER (10)
CALIBRATION REGISTER ADDRESS POINTER POSITION IS
DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS
ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.
Figure 5. Calibration Register Arrangement
–12–
REV. A

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