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AD7858L Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7858L
Beschreibung 3 V to 5 V Single Supply/ 200 kSPS 8-Channel/ 12-Bit Sampling ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 32 Seiten
AD7858L Datasheet, Funktion
a
3 V to 5 V Single Supply, 200 kSPS
8-Channel, 12-Bit Sampling ADC
FEATURES
Specified for VDD of 3 V to 5.5 V
AD7858—200 kSPS; AD7858L—100 kSPS
System and Self-Calibration with Autocalibration on
Power-Up
Eight Single-Ended or Four Pseudo-Differential Inputs
Low Power
AD7858: 12 mW (VDD = 3 V)
AD7858L: 4.5 mW (VDD = 3 V)
Automatic Power-Down After Conversion (25 W)
Flexible Serial Interface:
8051/SPI™/QSPI™/P Compatible
24-Lead DIP, SOIC, and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High-Speed Modems
GENERAL DESCRIPTION
The AD7858/AD7858L are high-speed, low-power, 12-bit
ADCs that operate from a single 3 V or 5 V power supply, the
AD7858 being optimized for speed and the AD7858L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system calibration options to en-
sure accurate operation over time and temperature and have a
number of power-down options for low-power applications.
The part powers up with a set of default conditions and can
operate as a read-only ADC.
The AD7858 is capable of 200 kHz throughput rate while the
AD7858L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a
pseudo-differential sampling scheme. The AD7858/AD7858L
voltage range is 0 to VREF with straight binary output coding.
Input signal range is to the supply and the part is capable of con-
verting full power signals to 100 kHz.
CMOS construction ensures low power dissipation of typically
4.5 mW for normal operation and 1.15 mW in power-down
mode with a throughput rate of 10 kSPS (VDD = 3 V). The part
is available in 24-lead, 0.3 inch-wide dual-in-line package
(DIP), 24-lead small outline (SOIC), and 24-lead small shrink
outline (SSOP) packages.
AD7858/AD7858L*
FUNCTIONAL BLOCK DIAGRAM
AIN1
AIN8
REFIN/REFOUT
CREF1
CREF2
CAL
AVDD
AGND
I/P
MUX
T/H
2.5V
REFERENCE
BUF
AD7858/
AD7858L
COMP
CHARGE
REDISTRIBUTION
DAC
CALIBRATION
MEMORY AND
CONTROLLER
SAR AND ADC
CONTROL
DVDD
DGND
CLKIN
CONVST
BUSY
SLEEP
SERIAL INTERFACE/CONTROL REGISTER
SYNC
DIN
DOUT SCLK
PRODUCT HIGHLIGHTS
1. Specified for 3 V and 5 V supplies.
2. Automatic calibration on power-up.
3. Flexible power management options including automatic
power-down after conversion.
4. Operates with reference voltages from 1.2 V to VDD.
5. Analog input range from 0 V to VDD.
6. Eight single-ended or four pseudo-differential input channels.
7. System and self-calibration.
8. Versatile serial I/O port (SPI/QSPI/8051/µP).
9. Lower power version AD7858L.
*Patent pending.
See page 31 for data sheet index.
SPI and QSPI are trademarks of Motorola, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






AD7858L Datasheet, Funktion
AD7858/AD7858L
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . ± 10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)
θJC Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7858/AD7858L features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Linearity Power
Error Dissipation Package
(LSB)1 (mW)
Options2
AD7858AN
±1
AD7858BN
± 1/2
AD7858LAN3
±1
AD7858LBN3
±1
AD7858AR
±1
AD7858BR
± 1/2
AD7858LAR3
±1
AD7858LBR3
±1
AD7858LARS3
±1
EVAL-AD7858CB4
EVAL-CONTROL BOARD5
20
20
6.85
6.85
20
20
6.85
6.85
6.85
N-24
N-24
N-24
N-24
R-24
R-24
R-24
R-24
RS-24
NOTES
1Linearity error here refers to integral linearity error.
2N = Plastic DIP; R = SOIC; RS = SSOP.
3L signifies the low-power version.
4This can be used as a stand-alone evaluation board or in conjunction with the EVAL-
CONTROL BOARD for evaluation/demonstration purposes.
5This board is a complete unit allowing a PC to control and communicate with all
Analog Devices evaluation boards ending in the CB designators.
PIN CONFIGURATIONS
DIP, SOIC, AND SSOP
CONVST 1
24 SYNC
BUSY 2
SLEEP 3
23 SCLK
22 CLKIN
REFIN/REFOUT 4
AVDD 5
21 DIN
AD7858/
AD7858L 20 DOUT
AGND 6 TOP VIEW 19 DGND
CREF1 7 (Not to Scale) 18 DVDD
CREF2 8
17 CAL
AIN1 9
16 AIN8
AIN2 10
AIN3 11
15 AIN7
14 AIN6
AIN4 12
13 AIN5
–6– REV. B

6 Page









AD7858L pdf, datenblatt
AD7858/AD7858L
STATUS REGISTER
The arrangement of the Status Register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits
in the status register are described below. The power-up status of all bits is 0.
START
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
Figure 6. Flowchart for Reading the Status Register
MSB
ZERO
BUSY
SGL/DIFF
CH2 CH1
CH0
PMGT1
PMGT0
RDSLT1 RDSLT0 2/3 MODE
X CALMD CALSLT1 CALSLT0
STCAL
LSB
STATUS REGISTER BIT FUNCTION DESCRIPTION
Bit
Mnemonic
Comment
15 ZERO
This bit is always 0.
14 BUSY
Conversion/Calibration Busy Bit. When this bit is 1, it indicates that there is a conversion
or calibration in progress. When this bit is 0, there is no conversion or calibration in progress.
13
SGL/DIFF
These four bits indicate the channel selected for conversion (see Table III).
12 CH2
11 CH1
10 CH0
9
PMGT1
Power management bits. These bits along with the SLEEP pin will indicate if the part is in a
8
PMGT0
power-down mode or not. See Table VI for description.
7
RDSLT1
Both of these bits are always 1, indicating it is the status register being read (see Table II).
6 RDSLT0
5
2/3 MODE
Interface Mode Select Bit. With this bit at 0, the device is in Interface Mode 2. With this bit at
1, the device is in Interface Mode 1. This bit is reset to 0 after every read cycle.
4X
Dont care bit.
3
CALMD
Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit
indicates a system calibration is selected (see Table IV).
2
CALSLT1
Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a
1
CALSLT0
calibration is in progress and as a 0 if there is no calibration in progress. The CALSLT1 and
0 STCAL CALSLT0 bits indicate which of the calibration registers are addressed for reading and writing
(see section on the Calibration Registers for more details).
–12–
REV. B

12 Page





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