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AD7851 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7851
Beschreibung 14-Bit 333 kSPS Serial A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD7851 Datasheet, Funktion
a
FEATURES
Single 5 V Supply
333 kSPS Throughput Rate/؎2 LSB DNL—A Grade
285 kSPS Throughput Rate/؎1 LSB DNL—K Grade
A & K Grades Guaranteed to 125؇C/238 kSPS
Throughput Rate
Pseudo-Differential Input with Two Input Ranges
System and Self-Calibration with Autocalibration on
Power-Up
Read/Write Capability of Calibration Data
Low Power: 60 mW typ
Power-Down Mode: 5 W typ Power Consumption
Flexible Serial Interface:
8051/SPI/QSPI/ P Compatible
24-Pin DIP, SOIC and SSOP Packages
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
DSP Servo Control
Instrumentation and Control Systems
High Speed Modems
Automotive
14-Bit 333 kSPS
Serial A/D Converter
AD7851
AIN (+)
AIN (–)
REFIN/
REFOUT
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
AGND
T/H
4.096 V
REFERENCE
BUF
AD7851
COMP
DVDD
DGND
AMODE
CREF1
CREF2
CAL
CHARGE
REDISTRIBUTION
DAC
CALIBRATION
MEMORY
AND CONTROLLER
SAR + ADC
CONTROL
CLKIN
CONVST
BUSY
SLEEP
SERIAL INTERFACE / CONTROL REGISTER
SM1 SM2 SYNC DIN DOUT SCLK POLARITY
GENERAL DESCRIPTION
The AD7851 is a high speed, 14-bit ADC that operates from a
single 5 V power supply. The ADC powers-up with a set of
default conditions at which time it can be operated as a read-
only ADC. The ADC contains self-calibration and system-
calibration options to ensure accurate operation over time and
temperature and has a number of power-down options for low
power applications.
The AD7851 is capable of 333 kHz throughput rate. The input
track-and-hold acquires a signal in 0.33 µs and features a
pseudo-differential sampling scheme. The AD7851 has the
added advantage of two input voltage ranges (0 V to VREF, and
–VREF/2 to +VREF/2 centered about VREF/2). Input signal range
is to VDD and the part is capable of converting full-power signals
to 20 MHz.
CMOS construction ensures low power dissipation (60 mW typ)
with power-down mode (5 µW typ). The part is available in 24-
pin, 0.3 inch-wide dual-in-line package (DIP), 24-lead small
outline (SOIC) and 24-lead small shrink outline (SSOP) packages.
PRODUCT HIGHLIGHTS
1. Single 5 V supply.
2. Operates with reference voltages from 4 V to VDD.
3. Analog input ranges from 0 V to VDD.
4. System and self-calibration including power-down mode.
5. Versatile serial I/O port.
*Patent pending.
See Page 35 for data sheet index.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD7851 Datasheet, Funktion
AD7851
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA
Operating Temperature Range
Commercial (A, K Versions) . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W
Lead Temperature, (Soldering, 10 secs) . . . . . . . . . . +260°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW
θJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)
θJC Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kV
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
PINOUT FOR DIP, SOIC AND SSOP
CONVST 1
24 SYNC
BUSY 2
23 SCLK
SLEEP 3
22 CLKIN
REFIN/REFOUT
AVDD
AGND
4
5
6
CREF1
CREF2
AIN(+)
7
8
9
AD7851
TOP VIEW
(Not to Scale)
21 DIN
20 DOUT
19 DGND
18 DVDD
17 CAL
16 SM2
AIN(–) 10
15 SM1
NC 11
14 POLARITY
AGND 12
13 AMODE
Model
Temp
Range
ORDERING GUIDE1
Linearity
Error
(LSB)2
Throughput
Rate
Throughput
@ +125؇C
Package
Options3
AD7851AN
AD7851KN
AD7851AR
AD7851KR
AD7851ARS
EVAL-AD7851CB4
EVAL-CONTROL BOARD5
–40°C to +85°C
0°C to +85°C
–40°C to +85°C
0°C to +85°C
–40°C to +85°C
±2
±1
±2
±1
±2
333 kSPS
285 kSPS
333 kSPS
285 kSPS
333 kSPS
238 kSPS
238 kSPS
238 kSPS
238 kSPS
238 kSPS
N-24
N-24
R-24
R-24
RS-24
NOTES
1Both A and K Grades are guaranteed up to 125°C, but at a lower throughput of 238 kHz (5 MHz)..
2Linearity error refers to the integral linearity error.
3N = Plastic DIP; R = SOIC; RS = SSOP.
4This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration
purposes.
5This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the
CB designators.
–6– REV. A

6 Page









AD7851 pdf, datenblatt
AD7851
CALIBRATION REGISTERS
The AD7851 has 10 calibration registers in all, 8 for the DAC, 1 for the offset and 1 for gain. Data can be written to or read from all
10 calibration registers. In self and system calibration the part automatically modifies the calibration registers; only if the user needs
to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-
dressed (see Table IV). The addressing applies to both the read and write operations for the calibration registers. The user should
not attempt to read from and write to the calibration registers at the same time.
CALSLT1 CALSLT0
00
01
10
11
Table IV. Calibration Register Addressing
Comment
This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.
This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.
This combination addresses the Offset Register. One register in total.
This combination addresses the Gain Register. One register in total.
Writing to/Reading from the Calibration Registers
For writing to the calibration registers a write to the control reg-
ister is required to set the CALSLT0 and CALSLT1 bits. For
reading from the calibration registers a write to the control reg-
ister is required to set the CALSLT0 and CALSLT1 bits, but
also to set the RDSLT1 and RDSLT0 bits to 10 (this addresses
the calibration registers for reading). The calibration register
pointer is reset on writing to the control register setting the
CALSLT1 and CALSLT0 bits, or upon completion of all the
calibration register write/read operations. When reset it points
to the first calibration register in the selected write/read
sequence. The calibration register pointer will point to the gain
calibration register upon reset in all but one case, this case be-
ing where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-
bration register is being accessed, the calibration register
pointer will be automatically incremented after each calibration
register write/read operation. The order in which the 10 calibra-
tion registers are arranged is shown in Figure 7. The user may
abort at any time before all the calibration register write/read
operations are completed, and the next control register write
operation will reset the calibration register pointer. The flow-
chart in Figure 8 shows the sequence for writing to the calibra-
tion registers and Figure 9 for reading.
CAL REGISTER
ADDRESS POINTER
CALIBRATION REGISTERS
GAIN REGISTER
OFFSET REGISTER
DAC 1st MSB REGISTER
(1)
(2)
(3)
DAC 8th MSB REGISTER (10)
CALIBRATION REGISTER ADDRESS POINTER POSITION IS
DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS
ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.
When reading from the calibration registers there will always be
two leading zeros for each of the registers. When operating in
serial Interface Mode 1, the read operations to the calibration
registers cannot be aborted. The full number of read operations
must be completed (see section on serial Interface Mode 1 tim-
ing for more detail).
START
WRITE TO CONTROL REGISTER SETTING STCAL = 0
AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
WRITE TO CAL REGISTER
(ADDR1 = 1, ADDR0 = 0)
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
?
YES
FINISHED
NO
Figure 8. Flowchart for Writing to the Calibration Registers
Figure 7. Calibration Register Arrangement
–12–
REV. A

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