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AD7849 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7849
Beschreibung 14-Bit/16-Bit DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD7849 Datasheet, Funktion
FEATURES
14-bit/16-bit multiplying DAC
Guaranteed monotonicity
Output control on power-up and power-down internal or
external control
Versatile serial interface
DAC clears to 0 V in both unipolar and bipolar output ranges
APPLICATIONS
Industrial process controls
PC analog I/O boards
Instrumentation
GENERAL DESCRIPTION
The AD7849 is a 14-bit/16-bit serial input multiplying digital-
to-analog converter (DAC). The DAC architecture ensures
excellent differential linearity performance, and monotonicity is
guaranteed to 14 bits for the A grade and to 16 bits for all other
grades over the specified temperature ranges.
During power-up and power-down sequences (when the supply
voltages are changing), the VOUT pin is clamped to 0 V via a low
impedance path. To prevent the output of A3 from being shorted to
0 V during this time, Transmission Gate G1 is also opened. These
conditions are maintained until the power supplies stabilize,
and a valid word is written to the DAC register. At this time, G2
opens and G1 closes. Both transmission gates are also externally
controllable via the reset in (RSTIN) control input. For instance, if
the RSTIN input is driven from a battery supervisor chip, then
at power-off or during a brown out, the RSTIN input is driven
low to open G1 and close G2. The DAC must be reloaded, with
RSTIN high, to reenable the output. Conversely, the on-chip
voltage detector output (RSTOUT) is also available to the user
to control other parts of the system.
Serial Input,
14-Bit/16-Bit DAC
AD7849
VREF+
R
R
VREF–
R
FUNCTIONAL BLOCK DIAGRAM
VDD
VCC
R
A1 R
G1
10-BIT/
12-BIT
DAC
10/
12
A3
G2
LOGIC
CIRCUITRY
A2 DAC
LATCH
4
10/
12
VOLTAGE
MONITOR
AD7849
INPUT
LATCH
INPUT SHIFT REGISTER/
CONTROL LOGIC
ROFS
RST IN
VOUT
AGND
RST OUT
DGND SDIN SCLK SYNC CLR BIN/ DCEN SDOUT LDAC VSS
COMP
Figure 1.
The AD7849 has a versatile serial interface structure and can be
controlled over three lines to facilitate opto-isolator applications.
SDOUT is the output of the on-chip shift register and can be
used in a daisy-chain fashion to program devices in the multi-
channel system. The daisy-chain enable (DCEN) input controls
this function.
The BIN/COMP pin sets the DAC coding; with BIN/COMP set
to 0, the coding is straight binary; and with BIN/COMP set to 1,
the coding is twos complement. This allows the user to reset the
DAC to 0 V in both the unipolar and bipolar output ranges.
The part is available in a 20-lead PDIP package and a 20-lead SOIC
package.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1995–2011 Analog Devices, Inc. All rights reserved.






AD7849 Datasheet, Funktion
AD7849
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to DGND
VCC to DGND1
VSS to DGND
VREF+ to DGND
VREF− to DGND
VOUT to DGND2
ROFS to DGND
Digital Input Voltage to DGND
Input Current to any Pin Except Supplies3
Operating Temperature Range
Storage Temperature Range
Junction Temperature
20-Lead PDIP
Power Dissipation
θJA Thermal Impedance
Lead Temperature (Soldering, 10 sec)
20-Lead SOIC
Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.4 V to +17 V
−0.4 V, VDD + 0.4 V or
+7 V (whichever is
lower)
−0.4 V to −17 V
VDD + 0.4 V, VSS − 0.4 V
VDD + 0.4 V, VSS − 0.4 V
VDD + 0.4 V, VSS − 0.4 V
or ±10 V (whichever is
lower)
VDD + 0.4 V, VSS − 0.4 V
−0.4 V to VCC + 0.4 V
±10 mA
−40°C to +85°C
−65°C to +150°C
150°C
875 mW
102°C/W
260°C
875 mW
74°C/W
215°C
220°C
1 VCC must not exceed VDD by more than 0.4 V. If it is possible for this to
happen during power-up or power-down (for example, if VCC is greater than
0.4 V while VDD is still 0 V), the following diode protection scheme ensures
protection.
VDD
VCC
1N4148
SD103C
1N5711
1N5712
VDD
VCC
AD7849
2 VOUT can be shorted to DGND, + 10 V, − 10 V, provided that the power
dissipation of the package is not exceeded.
3 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 6 of 20

6 Page









AD7849 pdf, datenblatt
AD7849
SCLK
SYNC
t2
t1
t3
BIN/COMP
SDIN
(AD7849B/C)
DB15
SDIN
(AD7849A)
DB13
t4 t5
t4 t5
DB0
DB0
LDAC, CLR
NOTES
1. DCEN IS TIED PERMANENTLY LOW.
Figure 16. Timing Diagram (Standalone Mode)
t7
DIGITAL INTERFACE
The AD7849 contains an input serial-to-parallel shift register and a
DAC latch. A simplified diagram of the input loading circuitry is
shown in Figure 16. Serial data on the SDIN input is loaded to
the input register under control of DCEN, SYNC and SCLK.
When a complete word is held in the shift register, it can then be
loaded into the DAC latch under control of LDAC. Only the data
in the DAC latch determines the analog output on the AD7849.
The daisy-chain enable (DCEN) input is used to select either the
standalone mode or the daisy-chain mode. The loading format
is slightly different depending on which mode is selected.
Serial Data Loading Format (Standalone Mode)
When DCEN is at Logic 0, standalone mode is selected. In this
mode, a low SYNC input provides the frame synchronization
signal that tells the AD7849 that valid serial data on the SDIN
input is available for the next 16 falling edges of SCLK. An internal
counter/decoder circuit provides a low gating signal so that only
16 data bits are clocked into the input shift register. After 16 SCLK
pulses, the internal gating signal goes inactive (high), thus locking
out any further clock pulses. Therefore, either a continuous clock
or a burst clock source can be used to clock in data.
The SYNC input is taken high after the complete 16-bit word is
loaded in.
The B version and C version are 16-bit resolution DACs and have a
straight 16-bit load format, with the MSB (DB15) being loaded
first. The A version is a 14-bit DAC; however, the loading structure
is still 16 bit. The MSB (DB13) is loaded first, and the final two
bits of the 16-bit stream must be 0s.
The DAC latch, and hence the analog output, can be updated in
two ways. The status of the LDAC input is examined after SYNC
is taken low. Depending on its status, one of two update modes
is selected.
If LDAC = 0, then automatic update mode is selected. In this mode,
the DAC latch and analog output are updated automatically when
the last bit in the serial data stream is clocked in. The update
thus takes place on the 16th falling SCLK edge.
If LDAC = 1, then automatic update mode is disabled. The DAC
latch update and output update are now separate. The DAC latch is
updated on the falling edge of LDAC. However, the output update
is delayed for a further 5 μs by means of an internal track-and-hold
amplifier in the output stage. This function results in a lower
digital-to-analog glitch impulse at the DAC output. Note that
the LDAC input must be taken back high again before the next
data transfer is initiated.
DCEN
SYNC
SCLK
SDIN
LDAC
CLR
RESET EN
÷16
COUNTER/
DECODER
GATED
SIGNAL
GATED
SCLK
INPUT
SHIFT REGISTER
(16 BITS)
AUTO-UPDATE
CIRCUITRY
DAC LATCH
(14/16 BITS)
SDOUT
Figure 17. Simplified Loading Structure
Rev. C | Page 12 of 20

12 Page





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