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AD7835 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7835
Beschreibung LC2MOS Quad 14-Bit DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD7835 Datasheet, Funktion
a
LC2MOS
Quad 14-Bit DAC
AD7834/AD7835
FEATURES
Four 14-Bit DACs in One Package
AD7834—Serial Loading
AD7835—Parallel 8-/14-Bit Loading
Voltage Outputs
Power-On Reset Function
Max/Min Output Voltage Range of +/–8.192 V
Maximum Output Voltage Span of 14 V
Common Voltage Reference Inputs
User Assigned Device Addressing
Clear Function to User-Defined Voltage
Surface Mount Packages
AD7834—28-Pin SO, DIP and Cerdip
AD7835—44-Pin PQFP and PLCC
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output volt-
ages in the range of ± 8.192 V with a maximum span of 14 V.
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading
0s, into one of the input latches via DIN, SCLK and FSYNC.
The AD7834 has five dedicated package address pins, PA0–
PA4, that can be wired to AGND or VCC to permit up to 32
AD7834s to be individually addressed in a multipackage
application.
The AD7835 can accept either 14-bit parallel loading or
double-byte loading, where right-justified data is loaded in one
8-bit and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the WR, CS,
BYSHF and DAC channel address pins, A0–A2.
With either device, the LDAC signal can be used to update
either all four DAC outputs simultaneously or individually,
on reception of new data. In addition, for either device, the
asynchronous CLR input can be used to set all signal outputs,
VOUT1–VOUT4, to the user-defined voltage level on the Device
Sense Ground pin, DSG. On power-on, before the power sup-
plies have stabilized, internal circuitry holds the DAC output
voltage levels to within ± 2 V of the DSG potential. As the sup-
plies stabilize, the DAC output levels move to the exact DSG
potential (assuming CLR is exercised).
The AD7834 is available in 28-pin 0.3" SO and 0.6" DIP pack-
ages, and the AD7835 is available in a 44-pin PQFP package
and a 44-pin PLCC package.
AD7834 FUNCTIONAL BLOCK DIAGRAM
VCC VDD VSS
VREF(–) VREF(+)
PAEN
PA0
PA1
PA2
PA3
PA4
FSYNC
DIN
SCLK
AD7834
CONTROL
LOGIC
&
ADDRESS
DECODE
SERIAL-TO-
PARALLEL
CONVERTER
INPUT
REGISTER
1
DAC 1
LATCH
INPUT
REGISTER
2
DAC 2
LATCH
DAC 1
DAC 2
INPUT
REGISTER
3
DAC 3
LATCH
DAC 3
INPUT
REGISTER
4
DAC 4
LATCH
DAC 4
AGND DGND
LDAC
DSG
X1
X1
X1
X1
VOUT 1
VOUT 2
VOUT 3
VOUT 4
CLR
AD7835 FUNCTIONAL BLOCK DIAGRAM
VCC VDD VSS
VREF(–)A VREF(+)A DSG A
BYSHF
DB13
DB0
WR
AD7835
INPUT 14
BUFFER
INPUT
REGISTER
1
DAC 1
LATCH
INPUT
REGISTER
2
DAC 2
LATCH
DAC 1
DAC 2
X1 VOUT 1
X1 VOUT 2
CS
A0
A1
ADDRESS
DECODE
A2
INPUT
REGISTER
3
DAC 3
LATCH
DAC 3
INPUT
REGISTER
4
DAC 4
LATCH
DAC 4
X1 VOUT 3
X1 VOUT 4
CLR
AGND DGND LDAC VREF(–)B VREF(+)B DSG B
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD7835 Datasheet, Funktion
AD7834/AD7835
Pin Mnemonic
VCC
VSS
VDD
DGND
AGND
VREF(+)A, VREF(–)A
VREF(+)B, VREF(–)B
VOUT1 . . . VOUT4
CS
DB0 . . . DB13
BYSHF
A0, A1, A2
LDAC
CLR
WR
DSGA
DSGB
Description
AD7835 PIN DESCRIPTION
Logic Power Supply; +5 V ± 5%.
Negative Analog Power Supply; –15 V ± 5%.
Positive Analog Power Supply; +15 V ± 5%.
Digital Ground.
Analog Ground.
Reference Inputs for DACs 1 and 2. These reference voltages are referred to AGND.
Reference Inputs for DACs 3 and 4. These reference voltages are referred to AGND.
DAC Outputs.
Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
Parallel Data Inputs. The AD7835 can accept a straight 14-bit parallel word on DB0 to DB13, where
DB13 is the MSB and the BYSHF input is hardwired to a logic high. Alternatively for byte loading, the
bottom 8 data inputs, DB0–DB7, are used for data loading while the top 6 data inputs, DB8 to DB13,
should be hardwired to a logic low. The BYSHF control input selects whether 8 LSBs or 6 MSBs of data
are being loaded into the device.
Byte Shift Input. When low, it shifts the data on DB0–DB7 into the DB8–DB13 half of the input register.
Address inputs. A0 and A1 are decoded to select one of the four input latches for a data transfer. A2 is
used to select all four DACs simultaneously.
Load DAC Input (level sensitive). This input signal in conjunction with the WR and CS input signals, de-
termines how the analog outputs are updated. If LDAC is maintained high while new data is being loaded
into the device’s input registers, no change occurs on the analog outputs. Subsequently, when LDAC is
brought low, the contents of all four input registers are transferred into their respective DAC latches, up-
dating the analog outputs simultaneously.
Alternatively, if LDAC is brought low while new data is being entered, then the addressed DAC latch
(and corresponding analog output) is updated immediately on the rising edge of WR.
Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs
are switched to the externally set potentials on the DSG pins (VOUT1 and VOUT2 follow DSGA while
VOUT3 and VOUT4 follow DSGB). When CLR is brought high, the signal outputs remain at the DSG po-
tentials until LDAC is brought low. When LDAC is brought low, the analog outputs are switched back to
reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored
and the signal outputs remain switched to the potential on the DSG pins.
Level-Triggered Write Input (active low). When active it is used in conjunction with CS to write data over
the input data bus.
Device Sense Ground A Input. Used in conjunction with the CLR input for power-on protection of the
DACs. When CLR is low, DAC outputs VOUT1 and VOUT2 are forced to the potential on the DSGA pin.
Device Sense Ground B Input. Used in conjunction with the CLR input for power-on protection of the
DACs. When CLR is low, DAC outputs VOUT3 and VOUT4 are forced to the potential on the DSGB pin.
–6– REV. A

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AD7835 pdf, datenblatt
AD7834/AD7835
The VREF pins should never be allowed to float when power is
applied to the part. (VREF(+) should never be allowed to go
below VREF(–)–0.3 V. VREF(–) should never be allowed to go
below VSS–0.3 V. VDD should never be allowed to go below
VCC–0.3 V.
In some systems it may be necessary to introduce one or more
Schottky diodes between pins to prevent the above situations
arising at power-on. These diodes are shown in Figure 19. How-
ever in most systems, with careful consideration given to power
supply sequencing, the above rules will be adhered to and pro-
tection diodes won’t be necessary.
VREF(+)
AD7834*
VREF(–)
SD103C
1N5711
1N5712
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Power-ON Protection
MICROPROCESSOR INTERFACING
AD7834 to 80C51 Interface
A serial interface between the AD7834 and the 80C51 micro-
controller is shown in Figure 20. TXD of the 80C51 drives
SCLK of the AD7834 while RXD drives the serial data line of
the part.
The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. The AD7834 expects the MSB of the
24-bit write first. Therefore, the user will have to ensure that
the data in the SBUF register is arranged correctly so that this is
taken into account. When data is to be transmitted to the part,
P3.3 is taken low. Data on RXD is valid on the falling edge of
TXD. The 80C51 transmits its data in 8-bit bytes with only 8
falling clock edges occurring in the transmit cycle. To load data
to the AD7834, P3.3 is left low after the first eight bits are
transferred. A second byte is then transferred, with P3.3 still
kept low. After the third byte has been transferred, the P3.3
line is taken high.
80C51*
P3.5
P3.4
P3.3
TXD
RXD
AD7834*
CLR
LDAC
FSYNC
SCLK
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. AD7834 to 80C51 Interface
LDAC and CLR on the AD7834 are also controlled by 80C51
port outputs. The user can bring LDAC low after every three
bytes have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the in-
put registers have been loaded (twelve byte transmits) and then
update the DAC outputs.
AD7834 to 68HC11 Interface
Figure 21 shows a serial interface between the AD7834 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7834 while the MOSI output drives the serial data line,
DIN, of the AD7834. The FSYNC signal is derived from port
line PC7 in this example.
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transferred to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes, MSB first. The AD7834 expects the MSB
of the 24-bit write first also. Eight falling clock edges occur in
the transmit cycle. To load data to the AD7834, PC7 is left low
after the first eight bits are transferred. A second byte of data is
then transmitted serially to the AD7834. Then a third byte is
transmitted, and when this transfer is complete, the PC7 line is
taken high.
68HC11*
PC5
PC6
PC7
SCK
MOSI
AD7834*
CLR
LDAC
FSYNC
SCLK
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7834 to 68HC11 Interface
In Figure 21, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7834 can be updated after each three-byte transfer, or else
all DACs can be simultaneously updated after twelve bytes have
been transferred.
AD7834 to ADSP-2101 Interface
An interface between the AD7834 and the ADSP-2101 is shown
in Figure 22. In the interface shown, SPORT0 is used to trans-
fer data to the part. SPORT1 is configured for alternate func-
tions. FO, the flag output on SPORT1, is connected to LDAC
and is used to load the DAC latches. In this way data can be
transferred from the ADSP-2101 to all the input registers in the
DAC and the DAC latches can be updated simultaneously. In
the application shown, the CLR pin on the AD7834 is con-
trolled by circuitry that monitors the power in the system.
ADSP-2101*
FO
TFS
SCK
DT
POWER
MONITOR
AD7834*
CLR
LDAC
FSYNC
SCLK
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. AD7834 to ADSP-2101 Interface
The AD7834 requires 24 bits of serial data framed by a single
FSYNC pulse. It is necessary that this FSYNC pulse stays low
until all the data has been transferred. This can be provided by
the ADSP-2101 in one of two ways. Both require setting the se-
–12–
REV. A

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