AD7834 Datasheet PDF - Analog Devices
| Part Number | AD7834 | |
| Description | LC2MOS Quad 14-Bit DAC | |
| Manufacturers | Analog Devices | |
| Logo |  |
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a
LC2MOS
Quad 14-Bit DAC
AD7834/AD7835
FEATURES
Four 14-Bit DACs in One Package
AD7834—Serial Loading
AD7835—Parallel 8-/14-Bit Loading
Voltage Outputs
Power-On Reset Function
Max/Min Output Voltage Range of +/–8.192 V
Maximum Output Voltage Span of 14 V
Common Voltage Reference Inputs
User Assigned Device Addressing
Clear Function to User-Defined Voltage
Surface Mount Packages
AD7834—28-Pin SO, DIP and Cerdip
AD7835—44-Pin PQFP and PLCC
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output volt-
ages in the range of ± 8.192 V with a maximum span of 14 V.
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading
0s, into one of the input latches via DIN, SCLK and FSYNC.
The AD7834 has five dedicated package address pins, PA0–
PA4, that can be wired to AGND or VCC to permit up to 32
AD7834s to be individually addressed in a multipackage
application.
The AD7835 can accept either 14-bit parallel loading or
double-byte loading, where right-justified data is loaded in one
8-bit and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the WR, CS,
BYSHF and DAC channel address pins, A0–A2.
With either device, the LDAC signal can be used to update
either all four DAC outputs simultaneously or individually,
on reception of new data. In addition, for either device, the
asynchronous CLR input can be used to set all signal outputs,
VOUT1–VOUT4, to the user-defined voltage level on the Device
Sense Ground pin, DSG. On power-on, before the power sup-
plies have stabilized, internal circuitry holds the DAC output
voltage levels to within ± 2 V of the DSG potential. As the sup-
plies stabilize, the DAC output levels move to the exact DSG
potential (assuming CLR is exercised).
The AD7834 is available in 28-pin 0.3" SO and 0.6" DIP pack-
ages, and the AD7835 is available in a 44-pin PQFP package
and a 44-pin PLCC package.
AD7834 FUNCTIONAL BLOCK DIAGRAM
VCC VDD VSS
VREF(–) VREF(+)
PAEN
PA0
PA1
PA2
PA3
PA4
FSYNC
DIN
SCLK
AD7834
CONTROL
LOGIC
&
ADDRESS
DECODE
SERIAL-TO-
PARALLEL
CONVERTER
INPUT
REGISTER
1
DAC 1
LATCH
INPUT
REGISTER
2
DAC 2
LATCH
DAC 1
DAC 2
INPUT
REGISTER
3
DAC 3
LATCH
DAC 3
INPUT
REGISTER
4
DAC 4
LATCH
DAC 4
AGND DGND
LDAC
DSG
X1
X1
X1
X1
VOUT 1
VOUT 2
VOUT 3
VOUT 4
CLR
AD7835 FUNCTIONAL BLOCK DIAGRAM
VCC VDD VSS
VREF(–)A VREF(+)A DSG A
BYSHF
DB13
DB0
WR
AD7835
INPUT 14
BUFFER
INPUT
REGISTER
1
DAC 1
LATCH
INPUT
REGISTER
2
DAC 2
LATCH
DAC 1
DAC 2
X1 VOUT 1
X1 VOUT 2
CS
A0
A1
ADDRESS
DECODE
A2
INPUT
REGISTER
3
DAC 3
LATCH
DAC 3
INPUT
REGISTER
4
DAC 4
LATCH
DAC 4
X1 VOUT 3
X1 VOUT 4
CLR
AGND DGND LDAC VREF(–)B VREF(+)B DSG B
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
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AD7834/AD7835
Pin Mnemonic Description
AD7834 PIN DESCRIPTION
VCC
VSS
VDD
DGND
AGND
VREF(+)
VREF(–)
VOUT1 . . . VOUT4
DSG
DIN
SCLK
FSYNC
PA0 . . . PA4
PAEN
LDAC
CLR
Logic Power Supply; +5 V ± 5%.
Negative Analog Power Supply; –15 V ± 5%.
Positive Analog Power Supply; +15 V ± 5%.
Digital Ground.
Analog Ground.
Positive Reference Input. The positive reference voltage is referred to AGND.
Negative Reference Input. The negative reference voltage is referred to AGND.
DAC Outputs.
Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of the DACs.
When CLR is low, the DAC outputs are forced to the potential on the DSG pin.
Serial Data Input.
Clock input for writing data to the device.
Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to the device
with serial data expected after the falling edge of this signal. The contents of the 24-bit serial-to-parallel input
register are transferred on the rising edge of this signal.
Package Address Inputs. These inputs are hardwired high (VCC) or low (DGND) to assign dedicated package
addresses in a multipackage environment.
Package Address Enable Input. When low, this input allows normal operation of the device. When it is high, the
device ignores the package address (but not the channel address) in the serial data stream and loads the serial
data into the input registers. This feature is useful in a multipackage application where it can be used to load the
same data into the same channel in each package.
Load DAC Input (level sensitive). This input signal in conjunction with the FSYNC input signal, determines
how the analog outputs are updated. If LDAC is maintained high while new data is being loaded into the
device’s input registers, no change occurs on the analog outputs. Subsequently, when LDAC is brought low, the
contents of all four input registers are transferred into their respective DAC latches, updating the analog outputs.
Alternatively, if LDAC is kept low while new data is shifted into the device, then the addressed DAC latch (and
corresponding analog output) is updated immediately on the rising edge of FSYNC.
Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs are
switched to the externally set potential on the DSG pin. When CLR is brought high, the signal outputs remain at
the DSG potential until LDAC is brought low. When LDAC is brought low, the analog outputs are switched
back to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored
and the signal outputs remain switched to the potential on the DSG pin.
PIN CONFIGURATION
DIP AND SOIC
VSS 1
DSG 2
28 AGND
27 NC
VREF(–) 3
26 NC
VREF(+) 4
25 NC
NC 5 AD7834 24 NC
VOUT2 6 TOP VIEW 23 VDD
VOUT4 7 (Not to Scale) 22 VOUT1
DGND 8
21 VOUT3
VCC 9
20 CLR
SCLK 10
19 LDAC
DIN 11
18 FSYNC
PA0 12
17 PAEN
PA1 13
16 PA4
PA2 14
15 PA3
NC = NO CONNECT
REV. A
–5–
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| Information | Total 16 Pages | |
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