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AD7825 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7825
Beschreibung 3 V/5 V/ 2 MSPS/ 8-Bit/ 1-/ 4-/ 8-Channel Sampling ADCs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 18 Seiten
AD7825 Datasheet, Funktion
a 3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel
Sampling ADCs
AD7822/AD7825/AD7829
FEATURES
8-Bit Half-Flash ADC with 420 ns Conversion Time
1, 4 and 8 Single-Ended Analog Input Channels
Available with Input Offset Adjust
On-Chip Track-and-Hold
SNR Performance Given for Input Frequencies Up to
10 MHz
On-Chip Reference (2.5 V)
Automatic Power-Down at the End of Conversion
Wide Operating Supply Range
3 V ؎ 10% and 5 V ؎ 10%
Input Ranges
0 V to 2 V p-p, VDD = 3 V ؎ 10%
0 V to 2.5 V p-p, VDD = 5 V ؎ 10%
Flexible Parallel Interface with EOC Pulse to Allow
Stand-Alone Operation
APPLICATIONS
Data Acquisition Systems, DSP Front Ends
Disk Drives
Mobile Communication Systems, Subsampling
Applications
FUNCTIONAL BLOCK DIAGRAM
CONVST EOC A0* A1* A2* PD*
VDD
CONTROL
LOGIC
COMP
2.5V
REF
VIN1
VIN2*
VIN3*
VIN4*
VIN5*
VIN6*
VIN7*
VIN8*
INPUT
MUX
T/H
8-BIT
HALF
FLASH
ADC
BUF
PARALLEL
PORT
VMID AGND DGND
*A0, A1
*A2
*PD
*VIN2 TO VIN4
*VIN4 TO VIN8
AD7825/AD7829
AD7829
AD7822/AD7825
AD7825/AD7829
AD7829
CS RD
VREFIN/REFOUT
DB7
DB0
GENERAL DESCRIPTION
The AD7822, AD7825, and AD7829 are high speed, 1-, 4-, and
8-channel, microprocessor-compatible, 8-bit analog-to-digital
converters with a maximum throughput of 2 MSPS. The AD7822,
AD7825, and AD7829 contain an on-chip reference of 2.5 V
(2% tolerance), a track/hold amplifier, a 420 ns 8-bit half-flash
ADC and a high speed parallel interface. The converters can
operate from a single 3 V ± 10% and 5 V ± 10% supply.
The AD7822, AD7825, and AD7829 combine the convert start
and power-down functions at one pin, i.e., the CONVST pin.
This allows a unique automatic power-down at the end of a
conversion to be implemented. The logic level on the CONVST
pin is sampled after the end of a conversion when an EOC (End
of Conversion) signal goes high, and if it is logic low at that
point, the ADC is powered down. The AD7822 and AD7825
also have a separate power-down pin. (See Operating Modes
section of the data sheet.)
The parallel interface is designed to allow easy interfacing to
microprocessors and DSPs. Using only address decoding logic,
the parts are easily mapped into the microprocessor address
space. The EOC pulse allows the ADCs to be used in a stand-
alone manner. (See Parallel Interface section of the data sheet.)
The AD7822 and AD7825 are available in a 20-/24-lead 0.3"
wide, plastic dual-in-line package (DIP), a 20-/24-lead small
outline IC (SOIC) and a 20-/24-lead thin shrink small outline
package (TSSOP). The AD7829 is available in a 28-lead 0.6"
wide, plastic dual-in-line package (DIP), a 28-lead small outline
IC (SOIC) and in a 28-lead thin shrink small outline package
(TSSOP).
PRODUCT HIGHLIGHTS
1. Fast Conversion Time
The AD7822, AD7825, and AD7829 have a conversion time
of 420 ns. Faster conversion times maximize the DSP pro-
cessing time in a real time system.
2. Analog Input Span Adjustment
The VMID pin allows the user to offset the input span. This
feature can reduce the requirements of single supply op amps
and take into account any system offsets.
3. FPBW (Full Power Bandwidth) of Track and Hold
The track-and-hold amplifier has an excellent high frequency
performance. The AD7822, AD7825, and AD7829 are
capable of converting full-scale input signals up to a fre-
quency of 10 MHz. This makes the parts ideally suited to
subsampling applications.
4. Channel Selection
Channel selection is made without the necessity of writing to
the part.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999






AD7825 Datasheet, Funktion
AD7822/AD7825/AD7829
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus, for an 8-bit converter, this is 50␣ dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7822/AD7825/AD7829
it is defined as:
THD (dB) = 20 log V22 +V32 +V42 +V52 +V62
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7822/AD7825/AD7829 are tested using the CCIF stan-
dard where two input frequencies near the top end of the input
bandwidth are used. In this case, the second and third order
terms are of different significance. The second order terms are
usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the intermodula-
tion distortion is as per the THD specification where it is the
ratio of the rms sum of the individual distortion products to the
rms amplitude of the fundamental expressed in dBs.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 20 kHz
sine wave signal to one input channel and determining how
much that signal is attenuated in each of the other channels.
The figure given is the worst case across all four or eight chan-
nels of the AD7825 and AD7829 respectively.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB change
between any two adjacent codes in the ADC.
Offset Error
The deviation of the 128th code transition (01111111) to
(10000000) from the ideal, i.e., VMID.
Offset Error Match
The difference in offset error between any two channels.
Zero-Scale Error
The deviation of the first code transition (00000000) to
(00000001) from the ideal, i.e., VMID – 1.25 V + 1 LSB (VDD =
5 V ± 10%), or VMID – 1.0 V + 1 LSB (VDD = 3 V ± 10%).
Full-Scale Error
The deviation of the last code transition (11111110) to
(11111111) from the ideal, i.e., VMID + 1.25 V – 1 LSB (VDD =
5 V ± 10%), or VMID + 1.0 V – 1 LSB (VDD = 3 V ± 10%).
Gain Error
The deviation of the last code transition (1111 . . . 110) to
(1111 . . . 111) from the ideal, i.e., VREF – 1 LSB, after the off-
set error has been adjusted out.
Gain Error Match
The difference in gain error between any two channels.
Track/Hold Acquisition Time
The time required for the output of the track/hold amplifier to
reach its final value, within ± 1/2 LSB, after the point at which
the track/hold returns to track mode. This happens approxi-
mately 120 ns after the falling edge of CONVST.
It also applies to situations where a change in the selected input
channel takes place or where there is a step input change on the
input voltage applied to the selected VIN input of the AD7822/
AD7825/AD7829. It means that the user must wait for the dura-
tion of the track/hold acquisition time after a channel change/step
input change to VIN before starting another conversion, to
ensure that the part operates to specification.
PSR (Power Supply Rejection)
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
CIRCUIT DESCRIPTION
The AD7822, AD7825, and AD7829 consist of a track-and-hold
amplifier followed by a half-flash analog-to-digital converter.
These devices use a half-flash conversion technique where one
4-bit flash ADC is used to achieve an 8-bit result. The 4-bit
flash ADC contains a sampling capacitor followed by fifteen
comparators that compare the unknown input to a reference
ladder to achieve a 4-bit result. This first flash, i.e., coarse con-
version, provides the 4 MSBs. For a full 8-bit reading to be
realized, a second flash, i.e., a fine conversion, must be per-
formed to provide the 4 LSBs. The 8-bit word is then placed on
the data output bus.
–6– REV. A

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AD7825 pdf, datenblatt
AD7822/AD7825/AD7829
OPERATING MODES
The AD7822, AD7825, and AD7829 have two possible modes
of operation, depending on the state of the CONVST pulse
approximately 100 ns after the end of a conversion, i.e., upon
the rising edge of the EOC pulse.
Mode 1 Operation (High Speed Sampling)
When the AD7822, AD7825, and AD7829 are operated in
Mode 1 they are not powered-down between conversions. This
mode of operation allows high throughput rates to be achieved.
Figure 20 shows how this optimum throughput rate is achieved
by bringing CONVST high before the end of a conversion, i.e.,
before the EOC pulses low. When operating in this mode a new
conversion should not be initiated until 30 ns after the end of a
read operation. This is to allow the track/hold to acquire the
analog signal to 0.5 LSB accuracy.
Mode 2 Operation (Automatic Power-Down)
When the AD7822, AD7825, and AD7829 are operated in
Mode 2 (see Figure 21), they automatically power down at the
end of a conversion. The CONVST signal is brought low to ini-
tiate a conversion and is left logic low until after the EOC goes
high, i.e., approximately 100 ns after the end of the conversion.
The state of the CONVST signal is sampled at this point (i.e.,
530 ns maximum after CONVST falling edge) and the AD7822,
AD7825, and AD7829 will power down as long as CONVST
is low. The ADC is powered up again on the rising edge of the
CONVST signal. Superior power performance can be achieved
in this mode of operation by only powering up the AD7822,
AD7825, and AD7829 to carry out a conversion. The parallel
interface of the AD7822, AD7825, and AD7829 is still fully
operational while the ADCs are powered down. A read may occur
while the part is powered down, and so it does not necessarily
need to be placed within the EOC pulse as shown in Figure 21.
TRACK
CONVST
EOC
120ns
HOLD
t2
t1
TRACK
HOLD
CS
RD
DB0-DB7
CONVST
EOC
CS
RD
DB0-DB7
tPOWER-UP
t3
VALID
DATA
Figure 20. Mode 1 Operation
POWER
DOWN
HERE
t1
VALID
DATA
Figure 21. Mode 2 Operation
–12–
REV. A

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