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AD7819 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7819
Beschreibung +2.7 V to +5.5 V/ 200 kSPS 8-Bit Sampling ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 11 Seiten
AD7819 Datasheet, Funktion
a
FEATURES
8-Bit ADC with 4.5 s Conversion Time
On-Chip Track and Hold
Operating Supply Range: +2.7 V to +5.5 V
Specifications at +2.7 V – 3.6 V and 5 V ؎ 10%
8-Bit Parallel Interface
8-Bit Read
Power Performance
Normal Operation
10.5 mW, VDD = 3 V
Automatic Power-Down
57.75 W @ 1 kSPS, VDD = 3 V
Analog Input Range: 0 V to VREF
Reference Input Range: 1.2 V to VDD
+2.7 V to +5.5 V, 200 kSPS
8-Bit Sampling ADC
AD7819
FUNCTIONAL BLOCK DIAGRAM
VDD AGND
VREF
AD7819
CHARGE
REDISTRIBUTION
DAC
CLOCK
OSC
THREE-
STATE
DRIVERS
DB7
DB0
VIN T/H
COMP
CONTROL
LOGIC
BUSY CS RD CONVST
GENERAL DESCRIPTION
The AD7819 is a high speed, microprocessor-compatible, 8-bit
analog-to-digital converter with a maximum throughput of
200 kSPS. The converter operates off a single +2.7 V to +5.5 V
supply and contains a 4.5 µs successive approximation A/D
converter, track/hold circuitry, on-chip clock oscillator and 8-bit
wide parallel interface. The parallel interface is designed to
allow easy interfacing to microprocessors and DSPs. Using only
address decoding logic the AD7819 is easily mapped into the
microprocessor address space.
When used in its power-down mode, the AD7819 automatically
powers down at the end of a conversion and powers up at the
start of a new conversion. This feature significantly reduces the
power consumption of the part at lower throughput rates. The
AD7819 can also operate in a high speed mode where the part is
not powered down between conversions. In this mode of opera-
tion the part is capable of providing 200 kSPS throughput.
The part is available in a small, 16-pin 0.3" wide, plastic dual-
in-line package (DIP); in a 16-pin, 0.15" wide, narrow body
small outline IC (SOIC) and in a 16-pin, narrow body, thin
shrink small outline package (TSSOP).
PRODUCT HIGHLIGHTS
1. Low Power, Single Supply Operation
The AD7819 operates from a single +2.7 V to +5.5 V sup-
ply and typically consumes only 10.5 mW of power. The
power dissipation can be significantly reduced at lower
throughput rates by using the automatic power-down mode.
2. Automatic Power-Down
The automatic power-down mode, whereby the AD7819
goes into power-down mode at the end of a conversion and
powers up before the next conversion, means the AD7819
is ideal for battery powered applications; e.g., 57.75 µW
@ 1 kSPS. (See Power vs. Throughput Rate section.)
3. Parallel Interface
An easy to use 8-bit wide parallel interface allows interfacing
to most popular microprocessors and DSPs with minimal
external circuitry.
4. Dynamic Specifications for DSP Users
In addition to the traditional ADC specifications, the AD7819
is specified for ac parameters, including signal-to-noise ratio
and distortion.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






AD7819 Datasheet, Funktion
AD7819
CIRCUIT DESCRIPTION
Converter Operation
The AD7819 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to VDD. Fig-
ures 2 and 3 below show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A, the comparator is held in a
balanced condition and the sampling capacitor acquires the sig-
nal on VIN+.
VIN
AGND
SAMPLING
A CAPACITOR
SW1
B
ACQUISITION
PHASE
VDD /3
CHARGE
RESTRIBUTION
DAC
SW2
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
Figure 2. ADC Track Phase
When the ADC starts a conversion, see Figure 3, SW2 will open
and SW1 will move to Position B causing the comparator to
become unbalanced. The Control Logic and the Charge Redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced the conversion is complete. The Control Logic generates
the ADC output code. Figure 7 shows the ADC transfer function.
SAMPLING
A CAPACITOR
VIN
SW1
B
CONVERSION
PHASE
AGND
VDD /3
CHARGE
RESTRIBUTION
DAC
SW2
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
Figure 3. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 4 shows a typical connection diagram for the AD7819. The
parallel interface is implemented using an 8-bit data bus, the
falling edge of CONVST brings the BUSY signal high and at
the end of conversion, the falling edge of BUSY is used to
initiate an ISR on a microprocessor. (See Parallel Interface
section for more details.) VREF is connected to a well decoupled
VDD pin to provide an analog input range of 0 V to VDD. When
VDD is first connected the AD7819 powers up in a low current
mode, i.e., power down. A rising edge on the CONVST input
will cause the part to power up. (See Power-Up Times section.)
If power consumption is of concern, the automatic power-down
at the end of a conversion should be used to improve power
performance. See Power vs. Throughput Rate section of the
data sheet.
SUPPLY
+2.7V TO +5.5V
10F
0V TO VREF
INPUT
0.1F
VDD VREF
PARALLEL
INTERFACE
DB0–DB7
AD7819
VIN BUSY
RD
GND
CS
CONVST
C/P
Figure 4. Typical Connection Diagram
Analog Input
Figure 5 shows an equivalent circuit of the analog input struc-
ture of the AD7819. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
20 mA is the maximum current these diodes can conduct with-
out causing irreversible damage to the part. The capacitor C2
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up of
the on resistance of a multiplexer and a switch. This resistor is
typically about 125 . The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
VDD
VIN
C2
4pF
D1 R1 C1
1253.5pF
VDD / 3
D2 CONVERT PHASE SWITCH OPEN
TRACK PHASE SWITCH CLOSED
Figure 5. Equivalent Analog Input Circuit
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver-
sion and ends on the falling edge of the CONVST signal. At the
end of a conversion there is a settling time associated with the
sampling circuit. This settling time lasts approximately 100 ns.
The analog signal on VIN is also being acquired during this
settling time. The minimum acquisition time needed is approxi-
mately 100 ns. Figure 6 shows the equivalent charging circuit
for the sampling capacitor when the ADC is in its acquisition
phase. R2 represents the source impedance of a buffer amplifier
or resistive network, R1 is an internal multiplexer resistance and
C1 is the sampling capacitor.
R2 VIN
R1
125
C1
3.5pF
Figure 6. Equivalent Sampling Circuit
6REV. A

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