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AD781 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD781
Beschreibung Complete 700 ns Sample-and-Hold Amplifier
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
AD781 Datasheet, Funktion
a
FEATURES
Acquisition Time to 0.01%: 700 ns Maximum
Low Power Dissipation: 95 mW
Low Droop Rate: 0.01 V/s
Fully Specified and Tested Hold Mode Distortion
Total Harmonic Distortion: –80 dB Maximum
Aperture Jitter: 75 ps Maximum
Internal Hold Capacitor
Self-Correcting Architecture
8-Pin Mini Cerdip and Plastic Package
MIL-STD-883 Compliant Versions Available
Complete 700 ns
Sample-and-Hold Amplifier
AD781*
FUNCTIONAL BLOCK DIAGRAM
VCC 1
IN 2
COMMON 3
NC 4
X1
AD781
8 OUT
7 S/H
6 NC
5 VEE
PRODUCT DESCRIPTION
The AD781 is a high speed monolithic sample-and-hold
amplifier (SHA). The AD781 guarantees a maximum
acquisition time of 700 ns to 0.01% over temperature. The
AD781 is specified and tested for hold mode total harmonic
distortion and hold mode signal-to-noise and distortion. The
AD781 is configured as a unity gain amplifier and uses a
self-correcting architecture that minimizes hold mode errors and
insures accuracy over temperature. The AD781 is self-contained
and requires no external components or adjustments.
The low power dissipation, 8-pin mini-DIP package and
completeness make the AD781 ideal for highly compact board
layouts. The AD781 will acquire a full-scale input in less than
700 ns and retain the held value with a droop rate of 0.01 µV/µs.
Excellent linearity and hold mode dc and dynamic performance
make the AD781 ideal for 12- and 14-bit high speed analog-
to-digital converters.
The AD781 is manufactured on Analog Devices’ BiMOS
process which merges high performance, low noise bipolar
circuitry with low power CMOS to provide an accurate, high
speed, low power SHA.
The AD781 is specified for three temperature ranges. The J
grade device is specified for operation from 0°C to +70°C, the A
grade from –40°C to +85°C and the S grade from –55°C to
+125°C. The J and A grades are available in 8-pin plastic DIP
packages. The S grade is available in an 8-pin cerdip package.
*Protected by U.S. Patent No. 4,962,325.
PRODUCT HIGHLIGHTS
1. Fast acquisition time (700 ns), low aperture jitter (75 ps) and
fully specified hold mode distortion make the AD781 an
ideal SHA for sampling systems.
2. Low droop (0.01 µV/µs) and internally compensated hold
mode error results in superior system accuracy.
3. Low power (95 mW typical), complete functionality and
small size make the AD781 an ideal choice for a variety of
high performance, low power applications.
4. The AD781 requires no external components or adjustments.
5. Excellent choice as a front-end SHA for high speed analog-
to-digital converters such as the AD671, AD7586, AD674B,
AD774B, AD7572 and AD7672.
6. Fully specified and tested hold mode distortion guarantees
the performance of the SHA in sampled data systems.
7. The AD781 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD781/883B data sheet for detailed
specifications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD781 Datasheet, Funktion
AD781
DYNAMIC PERFORMANCE
The AD781 is compatible with 12-bit A-to-D converters in
terms of both accuracy and speed. The fast acquisition time, fast
hold settling time and good output drive capability allow the
AD781 to be used with high speed, high resolution A-to-D
converters like the AD674 and AD7672. The AD781’s fast
acquisition time provides high throughput rates for multichannel
data acquisition systems. Typically, the sample and hold can
acquire a 10 V step in less than 600 ns. Figure 1 shows the
settling accuracy as a function of acquisition time.
0.08
0.06
(VOUT HOLD – VIN ), mV
+1
–5 –4 –3 –2 –1
VIN , VOLTS
1 2 3 4 +5
GAIN ERROR
HOLD MODE OFFSET
–1
NONLINEARITY
0.04
0.02
0
0 250 500 750 1000
ACQUISITION TIME – ns
Figure 1. VOUT Settling vs. Acquisition Time
The hold settling determines the required time, after the hold
command is given, for the output to settle to its final specified
accuracy. The typical settling behavior of the AD781 is shown
in Figure 2. The settling time of the AD781 is sufficiently fast to
allow the SHA, in most cases, to directly drive an A-to-D
converter without the need for an added “start convert” delay.
Figure 3. Hold Mode Offset, Gain Error and Nonlinearity
For applications where it is important to obtain zero offset, the
hold mode offset may be nulled externally at the input to the
A-to-D converter. Adjustment of the offset may be accom-
plished through the A-to-D itself or by an external amplifier
with offset nulling capability (e.g., AD711). The offset will
change less than 0.5 mV over the specified temperature range.
SUPPLY DECOUPLING AND GROUNDING
CONSIDERATIONS
As with any high speed, high resolution data acquisition system,
the power supplies should be well regulated and free from exces-
sive high frequency noise (ripple). The supply connection to the
AD781 should also be capable of delivering transient currents to
the device. To achieve the specified accuracy and dynamic per-
formance, decoupling capacitors must be placed directly at both
the positive and negative supply pins to common. Ceramic type
0.1 µF capacitors should be connected from VCC and VEE to
common.
ANALOG
P.S.
+12V
C –12V
DIGITAL
P.S.
C +5V
0.1µF 0.1µF
1µF 1µF
1µF
Figure 2. Typical AD781 Hold Mode
HOLD MODE OFFSET
The dc accuracy of the AD781 is determined primarily by the
hold mode offset. The hold mode offset refers to the difference
between the final held output voltage and the input signal at the
time the hold command is given. The hold mode offset arises
from a voltage error introduced onto the hold capacitor by
charge injection of the internal switches. The nominal hold
mode offset is specified for a 0 V input condition. Over the
input range of –5 V to +5 V, the AD781 is also characterized for
an effective gain error and nonlinearity of the held value, as
shown in Figure 3. As indicated by the AD781 specifications,
the hold mode offset is very stable over temperature.
INPUTS
AD781
+
7 9 11 15 1 DIGITAL
AD674
DATA
OUTPUT
SIGNAL GROUND
Figure 4. Basic Grounding and Decoupling Diagram
The AD781 does not provide separate analog and digital ground
leads as is the case with most A-to-D converters. The common
pin is the single ground terminal for the device. It is the refer-
ence point for the sampled input voltage and the held output
voltage and also the digital ground return path. The common
pin should be connected to the reference (analog) ground of the
A-to-D converter with a separate ground lead. Since the analog
and digital grounds in the AD781 are connected internally, the
–6– REV. A

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