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PDF AD7804 Data sheet ( Hoja de datos )
| Número de pieza | AD7804 | |
| Descripción | +3.3 V to +5 V Quad/Octal 10-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a +3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7804/AD7805/AD7808/AD7809*
FEATURES
Four 10-Bit DACs in One Package
Serial and Parallel Loading Facilities Available
AD7804 Quad 10-Bit Serial Loading
AD7805 Quad 10-Bit Parallel Loading
AD7808 Octal 10-Bit Serial Loading
AD7809 Octal 10-Bit Parallel Loading
+3.3 V to +5 V Operation
Power-Down Mode
Power-On Reset
Standby Mode (All DACs/Individual DACs)
Low Power All CMOS Construction
10-Bit Resolution
Double Buffered DAC Registers
Dual External Reference Capability
APPLICATIONS
Optical Disk Drives
Instrumentation and Communication Systems
Process Control and Voltage Setpoint Control
Trim Potentiometer Replacement
Automatic Calibration
GENERAL DESCRIPTION
The AD7804/AD7808 are quad/octal 10-bit digital-to-analog
converters, with serial load capabilities, while the AD7805/AD7809
are quad/octal 10-bit digital-to-analog converters with parallel
load capabilities. These parts operate from a +3.3 V to +5 V
(±10%) power supply and incorporates an on-chip reference.
These DACs provide output signals in the form of VBIAS ± VSWING.
VSWING is derived internally from VBIAS. On-chip control registers
include a system control register and channel control registers.
The system control register has control over all DACs in the
package. The channel control registers allow individual control
of DACs. The complete transfer function of each individual
DAC can be shifted around the VBIAS point using an on-chip
Sub DAC. All DACs contain double buffered data inputs,
which allow all analog outputs to be simultaneously updated
using the asynchronous LDAC input.
Control Features Channels Controlled Main DAC Sub DAC
Hardware Clear
System Control
Power Down1
System Standby2
System Clear
Input Coding
Channel Control
Channel Standby2
Channel Clear
VBIAS
All
All
All
All
All
Selective
Selective
Selective
͙͙
͙͙
͙͙
͙
͙͙
͙͙
͙
͙͙
NOTES
1Power-down function powers down all internal circuitry including the reference.
2Standby functions power down all circuitry except for the reference.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAMS
REFOUT
REFIN
COMP
1.23V REF
AVDD
DIVIDER
AVDD DVDD AGND DGND
POWER ON
RESET AD7804/
AD7808
VBIAS
MUX
DAC D
VOUTF*
VOUTE*
VOUTD
CHANNEL D
CONTROL REG
DATA
REGISTER
DAC
REGISTER
VBIAS
MUX
DAC C
VOUTC
CHANNEL C
CONTROL REG
DATA
REGISTER
DAC
REGISTER
VBIAS
MUX
DAC B
VOUTB
CHANNEL B
CONTROL REG
DATA
REGISTER
DAC
REGISTER
VBIAS
MUX
DAC A
PD**
CHANNEL A
CONTROL REG
DATA
REGISTER
DAC
REGISTER
FSIN
CLKIN
SDIN
SYSTEM
CONTROL REG
INPUT SHIFT
REGISTER &
CONTROL LOGIC
**ONLY AD7804 SHOWN FOR CLARITY
CLR LDAC
**SHOWS ADDITIONAL CHANNELS ON THE AD7808
**PIN ON THE AD7808 ONLY
VOUTA
VOUTH*
VOUTG*
REFOUT
REFIN
COMP
1.23V REF
AVDD
DIVIDER
AVDD DVDD AGND DGND
POWER ON
RESET
AD7805/
AD7809
VBIAS
MUX
DAC D
CHANNEL D
CONTROL REG
DATA
REGISTER
DAC
REGISTER
VBIAS
MUX
DAC C
VOUTF*
VOUTE*
VOUTD
VOUTC
CHANNEL C
CONTROL REG
DATA
REGISTER
DAC
REGISTER
VBIAS
MUX
DAC B
VOUTB
CHANNEL B
CONTROL REG
DATA
REGISTER
DAC
REGISTER
VBIAS
MUX
DAC A
VOUTA
PD**
CS
WR
CHANNEL A
CONTROL REG
DATA
DAC
REGISTER REGISTER
SYSTEM
CONTROL REG
CONTROL
LOGIC
INPUT
REGISTER
MODE A0 A1 A2** DB9 DB2 DB1 DB0 CLR LDAC
**ONLY AD7805 SHOWN FOR CLARITY
**SHOWS ADDITIONAL CHANNELS ON THE AD7809
**PIN ON THE AD7809 ONLY
*Patent pending.
Index on Page 26.
VOUTH*
VOUTG*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
AD7804/AD7805/AD7808/AD7809
AD7805/AD7809 TIMING CHARACTERISTICS1 (VDD= 3.3 V ؎ 10% to 5 V ؎ 10%; AGND = DGND = 0 V; Reference
= Internal Reference. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
All Versions
Unit
Description
t1 25
t2 4.5
t3 25
t4 4.5
t5 25
t6 4.5
t6A 6
t7 40
t8 0
t9 40
t10 100
t11 40
t12 100
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Mode Valid to Write Setup Time
Mode Valid to Write Hold Time
Address Valid to Write Setup Time
Address Valid to Write Hold Time
Data Setup Time
Data Hold Time
LDAC Valid to Write Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulsewidth
Time Between Successive Writes
LDAC, CLR Pulsewidth
Write to LDAC Setup Time
NOTE
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (VIL + VIH)/2.
Specifications subject to change without notice.
MODE
A0, A1, A2
t1
t2
t4
t3
CS
WR
DATA
LDAC 1
LDAC 2
t8
t7
t9
t5
t6
t6A
t12
t10
t11
CLR
t11
1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.
Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write
REV. A
–5–
5 Page 
AD7804/AD7805/AD7808/AD7809
VBIAS can be the internal bandgap reference, the internal VDD/2
reference or the external REFIN as determined by MX1 and
MX0 in the channel control register. A second external refer-
ence can be used if required by overdriving the VDD/2 reference
which appears at the COMP pin.
System Standby (SSTBY)
This bit allows all the DACs in the package to be put into low
power mode simultaneously but the reference is not affected.
Writing a one to the SSTBY bit in the system control register
puts all DACs into standby mode. On writing a one to this bit
all linear circuitry is switched off and the DAC outputs are
connected through a high impedance to ground. The DACs come
out of standby mode when a 0 is written to the SSTBY bit.
System Clear Function (SCLR)
This function allows the user to clear the contents of all data
and DAC registers in software. Writing a one to the SCLR bit
in the control register clears the DAC’s outputs. A zero in this
bit position puts the DAC in normal operating mode. The out-
put of the Main DACs are cleared to one of two voltages de-
pending on the input coding used. If twos complement coding
is selected, then issuing a software clear will reset the output of
the Main DAC to midscale (VBIAS). If offset binary coding is
selected, the Main DAC output will be reset to VBIAS /16 follow-
ing the execution of a software clear. This system clear function
does not affect the Sub DAC; the Sub DAC data register retains
its value during a system software clear (SCLR).
Standby (STBY)
This bit allows the selected DAC in the package to be put into
low power mode. Writing a zero to the STBY bit in the channel
control register puts the selected DAC into standby mode. On
writing a zero to this bit all linear circuitry is switched off and
the DAC output is connected through a high impedance to
ground. The DAC is returned to normal operation by writing a
one to the STBY bit.
Software Clear Function (CLR)
This function allows the user to clear the contents of the se-
lected DAC’s data in software. Writing a one to the CLR bit in
the control register clears the DAC’s output. A zero in the CLR
bit position puts the DAC in normal operating mode. This
software CLR operation clears only the Main DAC, the con-
tents of the Sub DAC is unaffected by a CLR operation. The
output of the Main DAC can be cleared to one of two places
depending on the input coding used. An LDAC pulse is re-
quired to activate the channel clear function and must be ap-
plied after the bit in the channel control register is set or reset. If
twos complement coding is selected, then issuing a software
clear will reset the output of the Main DAC to midscale (VBIAS).
If offset binary coding is selected, the Main DAC output will be
reset to VBIAS/16 following the execution of a software clear.
Multiplexer Selection (MX1, MX0)
These two bits are used to select the reference input for the
selected DAC. Table III shows the options available.
AD7804/AD7808 CHANNEL CONTROL REGISTER (MD1 = 0,
MD0 = 1)
This register allows the user to have control over individual
DACs in the package. The control bits in this register include
the address bits for the selected DAC, standby (STBY), indi-
vidual DAC clear (CLR) and multiplexer output selection
(MX1 and MX0). The function of these bits follows.
DAC Selection (A2, A1, A0)
Bits A2, A1 and A0 in the input registers are used to address a
specific DAC. Table IIa shows the selection table for the DACs
of the AD7804. Table IIb shows the selection table for the
DACs of the AD7808.
Table IIa. DAC Selection Table for the AD7804
A2 A1 A0 Function
X 0 0 DAC A Selected
X 0 1 DAC B Selected
X 1 0 DAC C Selected
X 1 1 DAC D Selected
Table IIb. DAC Selection Table for the AD7808
Table III. Multiplexer Output Selection
MX1
0
0
1
1
MX0
0
1
0
1
VBIAS
VDD/2
INTERNAL VREF
REFIN
Undetermined
AD7804/AD7808 SUB DAC DATA REGISTER
Figure 7 shows the loading sequence for writing to the data
registers of the DACs. DB15 determines whether writing is to
the Main or Sub DAC’s data register. A one in this position
selects the addressed Sub DAC’s data register. The Sub DAC is
8 bits wide and thus DB1 and DB0 of the 16-bit input word are
don’t cares when writing to the Sub DAC. This Sub DAC al-
lows the complete transfer function of each individual DAC to
be offset around the VBIAS point. This is achieved by either
adding or subtracting to the output of the Main DAC. This Sub
DAC has a span of ± VBIAS/32 with 1/8-bit resolution. The
coding scheme for the Sub DAC is the same as that for the
Main DAC. With offset binary coding the transfer function for
the Sub DAC is
A2 A1 A0 Function
0 0 0 DAC A Selected
0 0 1 DAC B Selected
0 1 0 DAC C Selected
0 1 1 DAC D Selected
1 0 0 DAC E Selected
1 0 1 DAC F Selected
1 1 0 DAC G Selected
1 1 1 DAC H Selected
REV. A
VBIAS
16
×
(
NB – 128
256
)
where NB is the digital code written to the Sub DAC and varies
from 0 to 255.
With twos complement coding the transfer function for the Sub
DAC is
( )VBIAS
16
×
NB
256
where NB is the digital code written to the Sub DAC and varies
from –128 to 127. VBIAS can be either the internal bandgap
reference, the internal VDD/2 reference or the external REFIN as
–11–
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD7804.PDF ] | |
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