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PDF AD7788 Data sheet ( Hoja de datos )
| Número de pieza | AD7788 | |
| Descripción | Low Power/ 16-/24-Bit Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
AD7788: 16-bit resolution
AD7789: 24-bit resolution
Power
Supply: 2.5 V to 5.25 V operation
Normal: 75 µA maximum
Power-down: 1 µA maximum
RMS noise: 1.5 µV
AD7788: 16-bit p-p resolution
AD7789: 19-bit p-p resolution (21.5 bits effective)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
VDD monitor channel
10-lead MSOP
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
Low Power, 16-/24-Bit
Sigma-Delta ADC
AD7788/AD7789
FUNCTIONAL BLOCK DIAGRAM
REFIN(+) REFIN(–) GND VDD
AD7788/
AD7789
CLOCK
AIN(+)
AIN(–)
Σ-∆
ADC*
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
*AD7788: 16-BIT ADC
AD7789: 24-BIT ADC
Figure 1.
03539-0-001
GENERAL DESCRIPTION
The AD7788/AD7789 are low power, low noise, analog front
ends for low frequency measurement applications. The AD7789
contains a low noise 24-bit ∑-∆ ADC with one differential input.
The AD7788 is a 16-bit version of the AD7789.
The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate is 16.6 Hz, which gives simultaneous 50 Hz/60 Hz
rejection.
The part operates with a single power supply from 2.5 V to
5.25 V. When operating from a 3 V supply, the power dissipation
for the part is 225 µW maximum. The AD7788/AD7789 is
housed in a 10-lead MSOP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD7788/AD7789
AD7788/AD7789 SPECIFICATIONS
Table 3.
Parameter
LOGIC INPUTS
All Inputs Except SCLK1
VINL, Input Low Voltage
VINH, Input High Voltage
SCLK Only (Schmitt-Triggered Input)1
VT(+)
VT(–)
VT(+) – VT(–)
VT(+)
VT(–)
VT(+) - VT(–)
Input Currents
Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage1
VOL, Output Low Voltage1
VOH, Output High Voltage1
VOL, Output Low Voltage1
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
POWER REQUIREMENTS2
Power Supply Voltage
VDD – GND
Power Supply Currents
IDD Current
IDD (Power-Down Mode)
AD7788A, B/
AD7789B
0.8
0.4
2.0
1.4/2
0.8/1.4
0.3/0.85
0.9/2
0.4/1.1
0.3/0.85
±1
10
VDD – 0.6
0.4
4
0.4
±1
10
Offset Binary
2.5/5.25
2.7/5.25
75
80
1
Unit
V max
V max
V min
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
µA max
pF typ
V min
V max
V min
V max
µA max
pF typ
V min/max
V min/max
µA max
µA max
µA max
Test Conditions/Comments
VDD = 5 V
VDD = 3 V
VDD = 3 V or 5 V
VDD = 5 V
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VDD = 3 V
VIN = VDD
All Digital Inputs
VDD = 3 V, ISOURCE = 100 µA
VDD = 3 V, ISINK = 100 µA
VDD = 5 V, ISOURCE = 200 µA
VDD = 5 V, ISINK = 1.6 mA
AD7789, AD7788B Grade
AD7788A Grade
65 µA typ, VDD = 3.6 V
73 µA typ, VDD = 5.25 V
1 Specification is not production tested but is supported by characterization data at initial product release.
2 Digital inputs equal to VDD or GND.
Rev. 0 | Page 5 of 20
5 Page 
AD7788/AD7789
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com-
munications register. The data written to the communications register determines whether the next operation is a read or write operation,
and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected
register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of
the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis-
ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to
this default state by resetting the entire part. Table 7 outlines the bit designations for the communications register. CR0 through CR7 indi-
cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.
CR7
WEN(0)
CR6
0(0)
CR5
RS1(0)
CR4
RS0(0)
CR3
R/W(0)
CR2
CREAD(0)
CR1
CH1(0)
CR0
CH0(0)
Table 7. Communications Register Bit Designations
Bit Location Bit Name
Description
CR7 WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits
will be loaded to the communications register.
CR6 0
This bit must be programmed with a Logic 0 for correct operation.
CR5–CR4
RS1–RS0
Register Address Bits. These address bits are used to select which of the ADC’s registers are being
selected during this serial interface communication. See Table 8.
CR3 R/W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this
position indicates that the next operation will be a read from the designated register.
CR2
CREAD
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the
serial interface is configured so that the data register can be continuously read, i.e., the contents of the
data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu-
nications register does not have to be written to for data reads. To enable continuous read mode, the
instruction 001111XX must be written to the communications register. To exit the continuous read
mode, the instruction 001110XX must be written to the communications register while the RDY pin is
low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on
DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to
the device.
CR1–CR0
CH1–CH0
These bits are used to select the analog input channel. The differential channel can be selected
(AIN(+)/AIN(–)) or an internal short (AIN(–)/AIN(–)) can be selected. Alternatively, the power supply can
be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring
power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for
conversion. The ADC uses a 1.17 V ± 5% on-chip reference as the reference source for the analog to
digital conversion. Any change in channel resets the filter and a new conversion is started.
Table 8. Register Selection
RS1 RS0 Register
0 0 Communications Register
during a Write Operation
0 0 Status Register during a
Read Operation
0 1 Mode Register
10
Reserved
11
Data Register
Register Size
8-Bit
8-Bit
8-Bit
8-Bit
16-Bit (AD7788)
24-Bit (AD7789)
Table 9. Channel Selection
CH1 CH0 Channel
0 0 AIN(+) – AIN(–)
0 1 Reserved
1 0 AIN(–) – AIN(–)
1 1 VDD Monitor
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD7788.PDF ] | |
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