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AD7769 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7769
Beschreibung LC2MOS Analog I/O Port
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD7769 Datasheet, Funktion
a
FEATURES
Two-Channel, 8-Bit 2.5 s ADC
Two 8-Bit, 2.5 s DACs with Output Amplifiers
Span and Offset of ADC and DAC
Independently Adjustable
Low Power
APPLICATIONS
Winchester Disk Servo Controllers
Floppy Disk Microstepping
Closed Loop Servo Systems
LC2MOS
Analog I/O Port
AD7769
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7769 is a complete, two-channel, 8-bit, analog I/O port.
It has versatile input and output signal conditioning features
that make it ideal for use in head-positioning servos in Winches-
ter disk systems. It is equally suitable for floppy disk microstep-
ping head positioning, other closed loop digital servo systems
and general purpose 8-bit data acquisition.
The AD7769 contains a high speed successive approximation
ADC, preceded by a two-channel multiplexer and signal condi-
tioning circuits. The input span of the ADC and the offset of
the zero point from ground can be independently set by apply-
ing ground referenced voltages. The AD7769 also contains two
independent, fast settling, 8-bit DACs with output amplifiers.
The output span and offset voltage of the DACs can be set inde-
pendently of those of the ADC. This makes the AD7769 espe-
cially useful in disk drives, where only a positive supply rail is
available and the ranges of the ADC and DACs must be refer-
enced to some positive voltage less than the supply.
The AD7769 is easily interfaced to a standard 8-bit mpu bus via
an 8-bit data port and standard microprocessor control lines.
The AD7769 is fabricated in Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
The part is available in a 28-lead plastic DIP and 28-terminal
PLCC package.
PRODUCT HIGHLIGHTS
1. Two-Channel, 8-Bit Analog I/O port on a Single Chip.
The AD7769 contains a two-channel, high speed ADC with
input signal conditioning and two, fast settling 8-bit DACs
with output amplifiers, on a single chip.
2. Independent Control of Span and Offset.
The input voltage span of the ADC and the midpoint of the
transfer function, the output voltage swing of the two DACs
and the half-scale output voltage, can be set independently
by applying ground referenced control voltages.
3. Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications,
the AD7769 is specified with ac parameters including signal-
to-noise ratio, distortion and signal bandwidth.
4. Fast Microprocessor Interface.
The AD7769 has bus interface timing compatible with all
modern microprocessors, with bus access and relinquish
times less than 65 ns and a Write pulse width less than 90 ns.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.comFax:
617/326-8703
© Analog Devices, Inc., 1997






AD7769 Datasheet, Funktion
AD7769
PIN FUNCTION DESCRIPTION
Pin Mnemonic
Description
1
2
3–10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD
VCC
DB7–DB0
INT
CLK
CHA/CHB
DGND
ADC/DAC
WR
RD
CS
VSWING (ADC)
AGND (ADC)
VINB
VBIAS (ADC)
VINA
AGND (DAC)
VSWING (DAC)
VOUTB
VBIAS (DAC)
VOUTA
+12 V Power Supply. This powers the analog circuitry.
+5 V Power Supply. This powers the logic circuitry.
Input/Output Data Bus. A bidirectional data port from which ADC output data may be read
and to which DAC input data may be written. DB7 is the Most Significant Bit.
Interrupt Output (active low). INT is set high on the falling edge of RD or WR to the ADC
and goes low at the end of a conversion.
Clock input. A clock is required for the ADC. An external TTL-compatible clock may be applied to
this input pin. Alternatively, tying this pin to VDD enables the internal clock oscillator. With an
external clock, the mark-space ratio can vary from 30/70 to 70/30.
Channel A/Channel B Select Input. Selects Channel A or Channel B of the DAC or ADC.
Used in conjunction with WR, RD, CS and ADC/DAC for read or write operations.
Digital Ground.
ADC or DAC Select Input. Selects either the ADC or the DAC for read or write operations in
conjunction with WR, RD, CS and CHA/CHB.
Write Input (edge triggered). This is used in conjunction with the ADC/DAC, CHA/CHB and CS
control inputs to start an ADC conversion or write data to the DAC. An ADC conversion starts on the
rising edge of WR.
Read Input (active low). This input must be low to access data from the ADC.
Chip Select Input (active low). The device is selected when this input is low.
ADC Reference Input. The voltage applied to this pin with respect to AGND (ADC) sets the
in put voltage Full-Scale Range (FSR) of the ADC. VIN (FSR) = 2 VSWING (ADC).
ADC Analog Ground.
Analog Input for Channel B. See VINA description.
ADC Reference Input. The voltage applied to this pin with respect to AGND (ADC) sets the
midpoint of the ADC transfer function.
Analog Input for Channel A. The input voltage range of both ADC channels is given by:
VIN A/B = VBIAS (ADC) ± VSWING (ADC).
DAC Analog Ground.
DAC Reference Input. The voltage applied to this pin with respect to AGND (DAC) sets the
output voltage Full-Scale Range (FSR) of the DACs. VOUT (FSR) = 2 VSWING (DAC).
Analog Output Voltage from DAC B. See VOUTA description.
DAC Reference Input. The voltage applied to this pin with respect to AGND (DAC) sets the
midpoint output voltage of the DACs.
Analog Output Voltage from DAC A. The output voltage range of both DACs is given by:
VOUT A/B = VBIAS (DAC) ± VSWING (DAC).
TERMINOLOGY
Relative Accuracy
For an ADC, Relative Accuracy or endpoint nonlinearity is the
maximum deviation, in LSBs, of the ADC’s actual code transi-
tion points from a straight line drawn between the endpoints of
the ADC transfer function, i.e., the 00 to 01 and FE to FF Hex
(01111111 to 11111111 Binary) code transitions.
For a DAC, Relative Accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func-
tion, i.e., those voltages which correspond to codes 00 and FF
Hex.
For the specified input and output ranges, 1 LSB = 19.5 mV,
but will vary with VSWING. For both DACs and ADC,
1 LSB = 2 VSWING /256 = FSR/256.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max en-
sures monotonicity (DAC) or no missed codes (ADC).
Bias Offset Error
For an ideal ADC, the output code for an input voltage equal to
VBIAS (ADC), should be 80 Hex (10000000 binary). The ADC
Bias Offset Error is the difference between the actual midpoint
voltage for code 80 Hex and VBIAS (ADC), expressed in LSBs.
For an ideal DAC, the output voltage for code 80 Hex should
be equal to VBIAS (DAC). The DAC Bias Offset Error is the
difference between the actual output voltage and VBIAS (DAC),
expressed in LSBs.
–6– REV. A

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AD7769 pdf, datenblatt
AD7769
Conversion is initiated on the selected AD7769 ADC channel
using a single I/O instruction, <OUT ADC, A>. The processor
then polls INT until it goes low before reading the conversion
result using an <IN A, ADC> instruction. Writing data to the rel-
evant AD7769 DAC consists of an <OUT DAC, A> instruction.
AD7769–ADSP-2101 Interface
Figure 19 shows a typical interface to the DSP microcomputer,
the ADSP-2101. The ADSP-2101 is optimized for high speed
numeric processing tasks.
Figure 20. AD7769 to 8051 (Processor Bus) Interface
Figure 19. AD7769 to ADSP-2101 Interface
Because the instruction cycle of the ADSP-2101 is very fast
(80 ns cycle), the WR and RD pulses must be stretched out to
suit the AD7769. This is easily achieved as the ADSP-2101
memory interface supports slower memories and memory-
mapped peripherals (i.e., AD7769) with a programmable wait
state generation capability. A number of wait states, from 0 to 7,
can be specified for each memory interface. One wait state is
sufficient for the interface to the AD7769.
AD7769–8051 Interface
A choice of two interface modes are available to the 8051
microcomputer.
Figure 20 shows a typical interface to the 8051 processor bus. It
is suitable for the maximum 8051 clock frequency of 12 MHz.
In this interface mode, Port 0 provides the multiplexed low or-
der address and data bus and Port 2 provides the high order ad-
dress bus (A8–A15).
Figure 21 shows the AD7769 interfaced to the 8051 parallel I/O
ports. This interface circuit is simpler to implement than the
previous interface to the processor bus, but, in general, the
maximum data throughput rate is much slower (for the same
clock frequencies). In addition to its simplicity, the interface to
the parallel I/O ports versus the processor bus allows indepen-
dent control of both the WR and RD inputs to the AD7769.
For example, the 8051 can set both WR and RD low at the
same time. This permits data from the last ADC conversion to
be written directly from the ADC register into the selected DAC
register (see Logic Truth Table). This allows very fast transfer
of data from the ADC to the DAC and is a useful feature for
some applications such as a fast, programmable, infinite sample-
and-hold function.
Figure 21. AD7769 to 8051 (Parallel l/O Ports) Interface
AD7769–MC68HC11 Interface
Figure 22 shows a typical interface between the AD7769 and the
MC68HC11 microcomputer. This interface is designed for the
maximum MC68HC11 clock speed of 8.4 MHz. The microcom-
puter is operated in the expanded multiplexed mode, with the
AD7769 as a memory mapped peripheral. The expansion bus is
made up of Ports B and C, and control signals AS and R/W.
Figure 22. AD7769 to MC68HC11 Interfaced
–12–
REV. A

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