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PDF AD7741 Data sheet ( Hoja de datos )
| Número de pieza | AD7741 | |
| Descripción | Single and Multichannel/ Synchronous Voltage-to-Frequency Converters | |
| Fabricantes | Analog Devices | |
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a
Single and Multichannel, Synchronous
Voltage-to-Frequency Converters
AD7741/AD7742
FEATURES
AD7741: One Single-Ended Input Channel
AD7742: Two Differential or Three Pseudo-Differential
Input Channels
Integral Nonlinearity of 0.012% at fOUT(Max) = 2.75 MHz
(AD7742) and at fOUT(Max) = 1.35 MHz (AD7741)
Single +5 V Supply Operation
Buffered Inputs
Programmable Gain Analog Front-End
On-Chip +2.5 V Reference
Internal/External Reference Option
Power Down to 35 A Max
Minimal External Components Required
8-Lead and 16-Lead DIP and SOIC Packages
APPLICATIONS
Low Cost Analog-to-Digital Conversion
Signal Isolation
GENERAL DESCRIPTION
The AD7741/AD7742 are a new generation of synchronous
voltage-to-frequency converters (VFCs). The AD7741 is a
single-channel version in an 8-lead package (SOIC/DIP) and the
AD7742 is a multichannel version in a 16-lead package (SOIC/
DIP). No user trimming is required to achieve the specified
performance.
The AD7741 has a single buffered input whereas the AD7742
has four buffered inputs that may be configured as two fully-
differential inputs or three pseudo-differential inputs. Both parts
include an on-chip +2.5 V bandgap reference that provides the
user with the option of using this internal reference or an exter-
nal reference.
FUNCTIONAL BLOCK DIAGRAMS
VDD REFIN/OUT
PD
VIN X1
+2.5V
REFERENCE
VOLTAGE-TO-
FREQUENCY
MODULATOR
POWER-DOWN
LOGIC
fOUT
CLOCK
GENERATION
AD7741
CLKIN CLKOUT
GND
GAIN
VIN1
VIN2
VIN3
VIN4
A1
A0
VDD UNI/BIP
PD
INPUT
MUX
X1/X2
AD7742
VOLTAGE-TO-
FREQUENCY
MODULATOR
POWER-DOWN
LOGIC
fOUT
CLOCK
GENERATION
+2.5V
REFERENCE
GND CLKIN CLKOUT REFIN REFOUT
The AD7741 has a single-ended voltage input range from 0 V
to REFIN. The AD7742 has a differential voltage input range
from –VREF to +VREF. Both parts operate from a single +5 V
supply consuming typically 6 mA, and also contain a power-
down feature that reduces the current consumption to less than
35 µA.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
Pin No.
1
Mnemonic
VDD
2 GND
3 CLKOUT
4 CLKIN
5 REFIN/OUT
6 VIN
7 PD
8 fOUT
AD7741/AD7742
AD7741 PIN FUNCTION DESCRIPTION
Function
Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should
be adequately decoupled to GND.
Ground reference point for all circuitry on the part.
External Clock Output. When the master clock for the device is a crystal, the crystal is connected
between CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pin
provides an inverted clock signal. This clock should be buffered if it is to be used as a clock source
elsewhere in the system.
External Clock Input. The master clock for the device can be provided in the form of a crystal or an
external clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the
CLKIN pin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The
frequency of the master clock may be as high as 6 MHz.
This is the reference input to the core of the VFC and defines the span of the VFC. If this pin is left
unconnected, the internal 2.5 V reference is used. Alternatively, a precision external reference (e.g.,
REF192) may be used to overdrive the internal reference. The internal bandgap reference has a
high output impedance in order to allow it to be overdriven.
The analog input to the VFC. It has an input range from 0 V to VREF. This input is buffered so it
draws virtually no current from whatever source is driving it.
Active Low Power-Down pin. When this input is low, the part enters power-down mode where it
typically consumes 15 µA of current.
Frequency Output. This pin provides the output of the synchronous VFC.
PIN CONFIGURATION
VDD 1
8 fOUT
GND 2 AD7741 7 PD
TOP VIEW
CLKOUT 3 (Not to Scale) 6 VIN
CLKIN 4
5 REFIN/OUT
REV. 0
–5–
5 Page 
Isolation Applications
In addition to analog-to-digital conversion, the AD7741/AD7742
can be used in isolated analog signal transmission applications.
Due to noise, safety requirements or distance, it may be neces-
sary to isolate the AD7741/AD7742 from any controlling
circuitry. This can easily be achieved by using opto-isolators,
which will provide isolation in excess of 3 kV.
Opto-electronic coupling is a popular method of isolated signal
coupling. In this type of device, the signal is coupled from an
input LED to an output photo-transistor, with light as the con-
necting medium. This technique allows dc to be transmitted, is
extremely useful in overcoming ground loops between equip-
ment, and is applicable over a wide range of speeds and power.
The analog voltage to be transmitted is converted to a pulse
train using the VFC. An opto-isolator circuit is used to couple
this pulse train across an isolation barrier using light as the
connecting medium. The input LED of the isolator is driven
from the output of the AD7741/AD7742. At the receiver side,
the output transistor is operated in the photo-transistor mode.
The pulse train can be reconverted to an analog voltage using a
frequency-to-voltage converter; alternatively, the pulse train can
be fed into a counter to generate a digital signal.
The analog and digital sections of the AD7741/AD7742 have
been designed to allow operation from a single-ended power
source, simplifying its use with isolated power supplies.
Figure 12 shows a general purpose VFC circuit using a low cost
opto-isolator. A +5 V power supply is assumed for both the
isolated (+5 V isolated) and local (+5 V local) supplies.
+5V VCC
VDD
R
IN AD774x
fOUT
OPTOCOUPLER
GND2
GND1
ISOLATION
BARRIER
Figure 12. Opto-Isolated Application
AD7741/AD7742
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board housing the
AD7741/AD7742 should be designed so the analog and digital
sections are separated and confined to certain areas of the board.
To minimize capacitive coupling between them, digital and
analog ground planes should only be joined in one place, close
to the DUT and should not overlap.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7742 to avoid noise coupling. The power
supply lines to the AD7742 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other parts of the board and clock signals should never
be run near analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at
right angles to each other. This reduces the effect of feedthrough
through the board. A microstrip technique is by far the best but
is not always possible with a double-sided board. In this tech-
nique, the component side of the board is dedicated to the ground
plane while the signal traces are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled to GND with surface mount capacitors, 10 µF in
parallel with 0.1 µF located as close to the package as possible,
ideally right up against the device. The lead lengths on the by-
pass capacitor should be as short as possible. It is essential that
these capacitors be placed physically close to the AD7741/AD7742
to minimize the inductance of the PCB trace between the ca-
pacitor and the supply pin. The 10 µF are the tantalum bead
type and are located in the vicinity of the VFC to reduce low-
frequency ripple. The 0.1 µF capacitors should have low Effec-
tive Series Resistance (ESR) and Effective Series Inductance
(ESI), such as the common ceramic types, which provide a low
impedance path to ground at high frequencies to handle tran-
sient currents due to internal logic switching. Additionally, it is
beneficial to have large capacitors (> 47 µF) located at the point
where the power connects to the PCB.
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD7741.PDF ] | |
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