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PDF AD7730 Data sheet ( Hoja de datos )
| Número de pieza | AD7730 | |
| Descripción | Bridge Transducer ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Bridge Transducer ADC
KEY FEATURES
Resolution of 230,000 Counts (Peak-to-Peak)
Offset Drift: 5 nV/؇C
Gain Drift: 2 ppm/؇C
Line Frequency Rejection: >150 dB
Buffered Differential Inputs
Programmable Filter Cutoffs
Specified for Drift Over Time
Operates with Reference Voltages of 1 V to 5 V
ADDITIONAL FEATURES
Two-Channel Programmable Gain Front End
On-Chip DAC for Offset/TARE Removal
FASTStep™ Mode
AC or DC Excitation
Single Supply Operation
APPLICATIONS
Weigh Scales
Pressure Measurement
GENERAL DESCRIPTION
The AD7730 is a complete analog front end for weigh-scale and
pressure measurement applications. The device accepts low-
level signals directly from a transducer and outputs a serial
digital word. The input signal is applied to a proprietary pro-
grammable gain front end based around an analog modulator.
AD7730/AD7730L
The modulator output is processed by a low pass programmable
digital filter, allowing adjustment of filter cutoff, output rate and
settling time.
The part features two buffered differential programmable gain
analog inputs as well as a differential reference input. The part
operates from a single +5 V supply. It accepts four unipolar
analog input ranges: 0 mV to +10 mV, +20 mV, +40 mV and
+80 mV and four bipolar ranges: ± 10 mV, ± 20 mV, ± 40 mV
and ± 80 mV. The peak-to-peak resolution achievable directly
from the part is 1 in 230,000 counts. An on-chip 6-bit DAC
allows the removal of TARE voltages. Clock signals for synchro-
nizing ac excitation of the bridge are also provided.
The serial interface on the part can be configured for three-wire
operation and is compatible with microcontrollers and digital
signal processors. The AD7730 contains self-calibration and
system calibration options, and features an offset drift of less
than 5 nV/°C and a gain drift of less than 2 ppm/°C.
The AD7730 is available in a 24-pin plastic DIP, a 24-lead
SOIC and 24-lead TSSOP package. The AD7730L is available
in a 24-lead SOIC and 24-lead TSSOP package.
NOTE
The description of the functions and operation given in this data
sheet apply to both the AD7730 and AD7730L. Specifications
and performance parameters differ for the parts. Specifications
for the AD7730L are outlined in Appendix A.
VBIAS
AIN1(+)
AIN1(–)
AIN2(+)/D1
AIN2(–)/D0
ACX
ACX
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
REF IN(–) REF IN(+)
REFERENCE DETECT
AD7730
AVDD
100nA
MUX
BUFFER
+
+/–
PGA
SIGMA-DELTA A/D CONVERTER
SIGMA-
DELTA
MODULATOR
PROGRAMMABLE
DIGITAL
FILTER
100nA
AGND
6-BIT
DAC
SERIAL INTERFACE
AND CONTROL LOGIC
CLOCK
GENERATION
REGISTER BANK
AC
EXCITATION
CLOCK
CALIBRATION
MICROCONTROLLER
AGND DGND
POL
RDY
RESET
STANDBY
SYNC
MCLK IN
MCLK OUT
SCLK
CS
DIN
DOUT
FASTStep is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –5 V to +0.3 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +5 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Reference Input Voltage to AGND . . –0.3 V to AVDD + 0.3 V
AIN/REF IN Current (Indefinite) . . . . . . . . . . . . . . . . 30 mA
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Output Voltage (ACX, ACX, D0, D1) to DGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
AD7730/AD7730L
Plastic DIP Package, Power Dissipation . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . +260°C
TSSOP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . 128°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
SOIC Package, Power Dissipation . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in
the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
ORDERING GUIDE
Model
AD7730BN
AD7730BR
AD7730BRU
EVAL-AD7730EB
AD7730LBR
AD7730LBRU
EVAL-AD7730LEB
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Evaluation Board
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Package
Description
Plastic DIP
Small Outline
Thin Shrink Small Outline
Small Outline
Thin Shrink Small Outline
Package
Options
N-24
R-24
RU-24
R-24
RU-24
ISINK (800A AT DVDD = +5V
100A AT DVDD = +3V)
TO OUTPUT
PIN
50pF
+1.6V
ISOURCE (200A AT DVDD = +5V
100A AT DVDD = +3V)
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7730 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–5–
5 Page 
AD7730/AD7730L
Table III. Output Noise vs. Input Range and Update Rate (CHP = 0)
Typical Output RMS Noise in nV
Output –3 dB
Data Rate Frequency
150 Hz
200 Hz
300 Hz
600 Hz
1200 Hz
5.85 Hz
7.8 Hz
11.7 Hz
23.4 Hz
46.8 Hz
SF
Word
2048
1536
1024
512
256
Settling Time
Normal Mode
166 ms
125 ms
83.3 ms
41.6 ms
20.8 ms
Settling Time
Fast Mode
26.6 ms
20 ms
13.3 ms
6.6 ms
3.3 ms
Input Range
= ؎80 mV
160
190
235
300
435
Input Range Input Range Input Range
= ؎40 mV = ؎20 mV = ؎10 mV
110 80
60
130 95
75
145 100 80
225 135 110
315 210 150
Table IV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0)
Peak-to-Peak Resolution in Counts (Bits)
Output –3 dB
Data Rate Frequency
150 Hz
200 Hz
300 Hz
600 Hz
1200 Hz
5.85 Hz
7.8 Hz
11.7 Hz
23.4 Hz
46.8 Hz
SF
Word
2048
1536
1024
512
256
Settling Time
Normal Mode
166 ms
125 ms
83.3 ms
41.6 ms
20.8 ms
Settling Time
Fast Mode
26.6 ms
20 ms
13.3 ms
6.6 ms
3.3 ms
Input Range
= ؎80 mV
165k (17.5)
140k (17)
115k (17)
90k (16.5)
60k (16)
Input Range Input Range Input Range
= ؎40 mV = ؎20 mV = ؎10 mV
120k (17)
100k (16.5)
90k (16.5)
60k (16)
43k (15.5)
80k (16.5)
70k (16)
65k (16)
50k (15.5)
32k (15)
55k (16)
45k (15.5)
40k (15.5)
30k (15)
20k (14.5)
ON-CHIP REGISTERS
The AD7730 contains thirteen on-chip registers which can be accessed via the serial port of the part. These registers are summarized
in Figure 4 and in Table V and described in detail in the following sections.
COMMUNICATIONS REGISTER
DIN DIN
RS2 RS1 RS0
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
STATUS REGISTER
DATA REGISTER
DIN
MODE REGISTER
DIN
FILTER REGISTER
DIN
DAC REGISTER
DIN
OFFSET REGISTER (x3)
DIN
GAIN REGISTER (x3)
DIN
TEST REGISTER
Figure 4. Register Overview
REGISTER
SELECT
DECODER
REV. A
–11–
11 Page | ||
| Páginas | Total 52 Páginas | |
| PDF Descargar | [ Datasheet AD7730.PDF ] | |
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