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AD7722 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7722
Beschreibung 16-Bit/ 195 kSPS CMOS/ Sigma-Delta ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD7722 Datasheet, Funktion
a
16-Bit, 195 kSPS
CMOS, Sigma-Delta ADC
AD7722
FEATURES
16-Bit Sigma-Delta ADC
64؋ Oversampling Ratio
Up to 220 kSPS Output Word Rate
Low-Pass, Linear Phase Digital Filter
Inherently Monotonic
On-Chip 2.5 V Voltage Reference
Single Supply +5 V
High Speed Parallel or Serial Interface
GENERAL DESCRIPTION
The AD7722 is a complete low power, 16-bit, sigma-delta
ADC. The part operates from a +5 V supply and accepts a
differential input voltage range of 0 V to +2.5 V or ± 1.25 V
centered around a common-mode bias. The AD7722 provides
16-bit performance for input bandwidths up to 90.625 kHz.
The part provides data at an output word rate of 195.3 kHz.
The analog input is continuously sampled by an analog modula-
tor eliminating the need for external sample-and-hold circuitry.
The modulator output is processed by two Finite Impulse
Response (FIR) digital filters in series. The on-chip filtering
reduces the external antialias requirements to first order, in
most cases. The group delay for the filter is 215.5 µs, while the
settling time for a step input is 431 µs. The sample rate, filter
corner frequency, and output word rate are set by an external
clock that is nominally 12.5 MHz.
Use of a single bit DAC in the modulator guarantees excellent
linearity and dc accuracy. Endpoint accuracy is ensured by on-
chip calibration. This calibration procedure minimizes the zero-
scale and full-scale errors.
FUNCTIONAL BLOCK DIAGRAM
DGND DVDD AGND AVDD REF1
VIN(+)
VIN(–)
P/S
CAL
RESET
SYNC
CS
DVAL/RD
CFMT/DRDY
DB0
DB1
DB2
AD7722
2.5V
REFERENCE
16-BIT A/D CONVERTER
Σ∆ FIR
MODULATOR FILTER
CLOCK
CIRCUITRY
CONTROL
LOGIC
REF2
XTAL
CLKIN
UNI
DB15
DB14
DB13
DB12
DB11
DB10
DB9/FSO
DB3/ DB4/ DB5/ DB6/ DB7/ DB8/
TSI DOE SFMT FSI SCO SDO
Conversion data is provided at the output register through a
flexible serial port or a parallel port. This offers 3-wire, high
speed interfacing to digital signal processors. The serial interface
operates in an internal clocking (master) mode, whereby an
internal serial data clock and framing pulse are device outputs.
Additionally, two AD7722s can be configured with the serial
data outputs connected together. Each converter alternately
transmits its conversion data on a shared serial data line.
The part provides an accurate on-chip 2.5 V reference. A
reference input/output function is provided to allow either the
internal reference or an external system reference to be used as
the reference source for the part.
The AD7722 is available in a 44-pin PQFP package and is
specified over the industrial temperature range from –40°C to
+85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996






AD7722 Datasheet, Funktion
AD7722
DOE
SDO
t15
t16
Figure 5. Serial Mode Timing for Data Output Enable and Serial Data Output (TSI = Logic Low)
DRDY
CS
RD
DB0 – DB15
t17 t18
t19 t25
t 20
t 21
t 24
t22 t23
VALID DATA
CLKIN
SYNC, RESET
DVAL
t 27
DRDY
Figure 6. Parallel Mode Read Timing
t 30
t 28
t 26
t 31
t 29
CLKIN
CAL
DVAL
DRDY
Figure 7. SYNC and RESET Timing, Serial and Parallel Mode
t 36
t 34
t 35
t 37
t 38
Figure 8. Calibration Timing, Serial and Parallel Mode
–6– REV. 0

6 Page









AD7722 pdf, datenblatt
AD7722–Typical Characteristics
(AVDD = DVDD = 5.0 V, TA = +25؇C; CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode; VIN(+) = 0 V to 2.5 V, VIN(–) = 1.25 V unless otherwise noted)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
20000
40000
CODE
65535
200
180
160
140
120
100
80
60
40
20
0
0
AIDD
D IDD
2.5 5 7.5 10 12.5 15
CLKIN FREQUENCY – MHz
Figure 18. Integral Nonlinearity Error
Figure 21. Power Consumption vs.
CLKIN Frequency
0
–20
–40
–60
–80
–100
CLKIN = 12.5MHz
SNR = 90.1dB
S/(N+D) = 89.2dB
SFDR = –99.5dB
THD = –96.6dB
2ND = –100.9dB
3RD = –106.0dB
4TH = –99.5dB
–120
–140
–154
0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 98E+3
Figure 19. 16K Point FFT
0
–20
–40
–60
–80
–100
XTAL = 12.288MHz
SNR = 89.0dB
S/(N+D) = 87.8dB
SFDR = –94.3dB
THD = –93.8dB
2ND = –94.3dB
3RD = –108.5dB
4TH = –105.7dB
–120
–140
–154
0E+0
10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3
80E+3 90E+3 96E+3
Figure 20. 16K Point FFT
0
–20 AIN = 90kHz
CLKIN = 12.5 MHz
–40 SNR = 89.6dB
S/(N+D) = 89.6dB
–60 SFDR = –108.0dB
–80
–100
–120
–140
–154
0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 98E+3
Figure 22. 16K Point FFT
0
–20 AIN = 90kHz
XTAL = 12.288MHz
–40 SNR = 88.1dB
S/(N+D) = 88.1dB
–60 SFDR = –103.7dB
–80
–100
–120
–140
–154
0E+0
10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3
80E+3 90E+3 96E+3
Figure 23. 16K Point FFT
–12–
REV. 0

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