|
|
PDF AD7721 Data sheet ( Hoja de datos )
| Número de pieza | AD7721 | |
| Descripción | CMOS 16-Bit/ 468.75 kHz/ Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD7721 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
a
CMOS 16-Bit,
468.75 kHz, Sigma-Delta ADC
AD7721
FEATURES
16-Bit Sigma-Delta ADC
468.75 kHz Output Word Rate (OWR)
No Missing Codes
Low-Pass Digital Filter
High Speed Serial Interface
Linear Phase
229.2 kHz Input Bandwidth
Power Supplies: AVDD, DVDD: +5 V ؎ 5%
Standby Mode (70 W)
Parallel Mode (12-Bit/312.5 kHz OWR)
GENERAL DESCRIPTION
The AD7721 is a complete low power, 12-/16-bit, sigma-delta
ADC. The part operates from a +5 V supply and accepts a
differential input of 0 V to 2.5 V or ± 1.25 V. The analog input
is continuously sampled by an analog modulator at twice the
clock frequency eliminating the need for external sample-and-
hold circuitry. The modulator output is processed by two finite
impulse response (FIR) digital filters in series. The on-chip
filtering reduces the external antialias requirements to first order
in most cases. Settling time for a step input is 97.07 µs while
the group delay for the filter is 48.53 µs when the master clock
equals 15 MHz.
The AD7721 can be operated with input bandwidths up to
229.2 kHz. The corresponding output word rate is 468.75 kHz.
The part can be operated with lower clock frequencies also.
The sample rate, filter corner frequency and output word rate
will be reduced also, as these are proportional to the external
clock frequency. The maximum clock frequencies in parallel
mode and serial mode are 10 MHz and 15 MHz respectively.
FUNCTIONAL BLOCK DIAGRAM
DGND
DGND
DSUBST
VIN1
VIN2
DVAL/SYNC
CS
RD
WR
STBY/DB0
CAL/DB1
UNI/DB2
AGND AGND
AVDD
DVDD
AD7721
12-BIT A/D CONVERTER
⌺-⌬
MODULATOR
FIR
FILTER
CONTROL LOGIC
REFIN
CLK
DRDY
SDATA/DB11
RFS/DB10
DB9
DB3 DB4 SYNC/ DB6 SCLK/ DB8
DB5
DB7
Use of a single bit DAC in the modulator guarantees excellent
linearity and dc accuracy. Endpoint accuracy is ensured by on-
chip calibration of offset and gain. This calibration procedure
minimizes the part’s zero-scale and full-scale errors.
The output data is accessed from the output register through a
serial or parallel port. This offers easy, high speed interfacing to
modern microcontrollers and digital signal processors. The
serial interface operates in internal clocking (master) mode, the
AD7721 providing the serial clock.
CMOS construction ensures low power dissipation while a
power-down mode reduces the power consumption to only
100 µW.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
1 page  
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise stated)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Input Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . ± 10 mA
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Plastic Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
AD7721
Lead Temperature, Soldering (10 sec) . . . . . . . . . . +260°C
Cerdip Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 51°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . +300°C
SOIC Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 72°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latchup.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature Range Package Option*
AD7721AN
AD7721AR
AD7721SQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-28
R-28
Q-28
*N = Plastic DIP; R = 0.3" Small Outline IC (SOIC); Q = Cerdip.
PIN CONFIGURATION
SCLK/DB7 1
28 DB6
DB8 2
27 RD
DB9 3
26 WR
RFS/DB10 4
25 DVAL/SYNC
SDATA/DB11 5 AD7721 24 AGND
DGND 6 TOP VIEW 23 VIN2
DSUBST 7 (Not to Scale) 22 VIN1
DGND 8
21 REFIN
STBY/DB0 9
20 AGND
DVDD 10
19 AVDD
CAL/DB1 11
UNI/DB2 12
DB3 13
DB4 14
18 CS
17 CLK
16 DRDY
15 SYNC/DB5
REV. A
–5–
5 Page 
CIRCUIT DESCRIPTION
Sigma-Delta ADC
The AD7721 ADC employs a sigma-delta conversion technique
that converts the analog input into a digital pulse train.
Due to the high oversampling rate, which spreads the quantiza-
tion noise from 0 to fCLK/2, the noise energy which is contained
in the band of interest is reduced (Figure 8a). To reduce the
quantization noise further, a high order modulator is employed
to shape the noise spectrum, so that most of the noise energy is
shifted out of the band of interest (Figure 8b).
The digital filter that follows the modulator removes the large
out of band quantization noise (Figure 8c), while converting the
digital pulse train into parallel 12 bit wide binary data or serial
16 bit wide binary data.
AD7721
a linear phase response. This is very difficult to achieve with
analog filters.
Analog filters, however, can remove noise superimposed on the
signal before it reaches the ADC. Digital filtering cannot do this
and noise peaks riding on signals, near full-scale, have the po-
tential to overload the analog modulator even though the aver-
age value of the signal is within limits.
0.0
–50.0
QUANTIZATION NOISE
BAND OF
INTEREST
a.
fCLK/ 2
–100.0
–150.0
0.0fCLK
0.1fCLK
0.2fCLK
0.3fCLK
FREQUENCY
0.4fCLK
0.5fCLK
Figure 9a. 128 Tap FIR Filter Frequency Response
BAND OF
INTEREST
NOISE
SHAPING
b.
fCLK/ 2
0.0
–50.0
DIGITAL FILTER CUTOFF FREQUENCY
WHICH EQUALS 152.8kHz (10MHz) OR
229.2kHz (15MHz)
–100.0
BAND OF
INTEREST
fCLK/ 2
c.
Figure 8. Sigma-Delta ADC
Digital Filter
The digital filter that follows the modulator removes the large
out of band quantization noise, while converting the one bit
digital pulse train into 12-bit or 16-bit wide binary data. The
digital filter also reduces the data rate from fCLK at the input of
the filter to fCLK/32 at the output of the filter. The output data
rate is a little over twice the signal bandwidth which guarantees
that there is no loss of data in the signal band.
The AD7721 employs 2 FIR filters in series. The first filter is a
128 tap filter that samples the output of the modulator at fCLK.
The second filter is an 83 tap half-band filter that samples the
output of the first filter at fCLK/16 and decimates by 2. The
frequency response of the 2 filters is shown in Figure 9.
Digital filtering has certain advantages over analog filtering.
First, since digital filtering occurs after the A/D conversion, it
can remove noise injected during the conversion process. Ana-
log filtering cannot do this. Second, the digital filter combines
low passband ripple with a steep roll off, while also maintaining
–150.0
0.0fCLK/32 0.2fCLK/32 0.4fCLK/32 0.6fCLK/32 0.8fCLK/32 1.0fCLK/32
FREQUENCY
Figure 9b. 83 Tap FIR Filter Frequency Response
SERIAL INTERFACE
The AD7721’s serial communication port allows easy inter-
facing to industry-standard microprocessors, microcontrollers
and digital signal processors. The AD7721 is operated in self-
clocking mode, the AD7721 providing the serial clock. The
RFS signal is also provided by the AD7721 by tying RFS to
DRDY.
Figure 10 shows the timing diagram for reading from the
AD7721. DRDY goes high to indicate that a conversion has
been completed. DRDY remains high for one internal clock
(15 MHz) cycle and then goes low for the next 31 clock cycles.
New data is loaded into the output shift register on the rising
edge of DRDY. When DRDY goes low, the data is accessed
from the AD7721. Although the AD7721 has a 12-bit digital
output in the parallel mode, sixteen bits of data are available for
transmission in the serial mode, starting with the MSB. Serial
data is clocked out of the device on the rising edge of SCLK
and is valid on the falling edge of SCLK.
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7721.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD7720 | CMOS Sigma-Delta Modulator | Analog Devices |
| AD7721 | CMOS 16-Bit/ 468.75 kHz/ Sigma-Delta ADC | Analog Devices |
| AD7722 | 16-Bit/ 195 kSPS CMOS/ Sigma-Delta ADC | Analog Devices |
| AD7723 | 16-Bit/ 1.2 MSPS CMOS/ Sigma-Delta ADC | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |