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PDF AD7676 Data sheet ( Hoja de datos )
| Número de pieza | AD7676 | |
| Descripción | 16-Bit +-1 LSB INL/ 500 kSPS/ Differential ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Throughput: 500 kSPS
INL: ؎1 LSB Max (؎0.0015% of Full-Scale)
16 Bits Resolution with No Missing Codes
S/(N+D): 94 dB Typ @ 45 kHz
THD: –110 dB Typ @ 45 kHz
Differential Input Range: ؎2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel (8/16 Bits) and Serial 5 V/3 V Interface
SPI™/QSPI™/MICROWIRE™/DSP Compatible
Single 5 V Supply Operation
67 mW Typical Power Dissipation, 15 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flat Pack (LQFP)
Pin-to-Pin Compatible with the AD7675
APPLICATIONS
CT Scanners
Data Acquisition
Instrumentation
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
16-Bit, ؎1 LSB INL,
500 kSPS, Differential ADC
AD7676*
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND REF REFGND
DVDD DGND
IN+
IN–
PD
RESET
AD7676
SWITCHED
CAP DAC
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
SERIAL
PORT
16
PARALLEL
INTERFACE
CNVST
OVDD
OGND
SER/PAR
BUSY
DATA[15:0]
CS
RD
OB/2C
BYTESWAP
GENERAL DESCRIPTION
The AD7676 is a 16-bit, 500 kSPS, charge redistribution SAR,
fully differential analog-to-digital converter that operates from a
single 5 V power supply. The part contains a high-speed 16-bit
sampling ADC, an internal conversion clock, error correction
circuits, and both serial and parallel system interface ports.
The AD7676 is hardware factory calibrated and is comprehensively
tested to ensure such ac parameters as signal-to-noise ratio (SNR)
and total harmonic distortion (THD), in addition to the more
traditional dc parameters of gain, offset, and linearity.
It is fabricated using Analog Devices’ high-performance, 0.6
micron CMOS process and is available in a 48-lead LQFP with
operation specified from –40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Excellent INL
The AD7676 has a maximum integral nonlinearity of 1.0 LSB
with no missing 16-bit code.
2. Superior AC Performances
The AD7676 has a minimum dynamic of 92 dB, 94 dB typical.
3. Fast Throughput
The AD7676 is a 500 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
4. Single-Supply Operation
The AD7676 operates from a single 5 V supply and typically
dissipates only 67 mW. It consumes 7 µW maximum when in
power-down.
5. Serial or Parallel Interface
Versatile parallel (8 or 16 bits) or 2-wire serial interface
arrangement compatible with either 3 V or 5 V logic.
*Patent pending
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
Pin No.
1
2
3, 6, 7,
40–42,
44–48
4
Mnemonic
AGND
AVDD
NC
BYTESWAP
Type
P
P
DI
5 OB/2C DI
8
9, 10
11, 12
SER/PAR
DI
DATA[0:1]
DO
DATA[2:3] or DI/O
DIVSCLK[0:1]
13
DATA[4]
DI/O
or EXT/INT
14
DATA[5]
DI/O
or INVSYNC
15
DATA[6]
DI/O
or INVSCLK
16
DATA[7]
DI/O
or RDC/SDIN
17 OGND
18 OVDD
19 DVDD
20 DGND
P
P
P
P
PIN FUNCTION DESCRIPTIONS
Description
Analog Power Ground Pin
Input Analog Power Pins. Nominally 5 V.
No Connect
AD7676
Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB
is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output
on D[7:0].
Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs
are in high impedance.
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the
serial master read-after-convert mode. These inputs, part of the serial port, are used to slow
down, if desired, the internal serial clock which clocks the data output. In the other serial
modes, these inputs are not used.
When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal
clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is
synchronized to an external clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state
of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK
signal. It is active in both master and slave mode.
When SER/PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as either an external
data input or a read mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the
conversion results from two or more ADCs onto a single SDOUT line. The digital data
level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of
the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode.
When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When
RDC/SDIN is LOW, the data isoutput on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power Ground
Input/Output Interface Digital Power. Nominally at the same supply than the supply of the
host interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
Digital Power Ground
REV. 0
–5–
5 Page 
ANALOG
SUPPLY
(5V)
+ 10F 100nF
100⍀
NOTE 5
+ 10F
DVDD
100nF
AD7676
100nF + 10F
DIGITAL SUPPLY
(3.3V OR 5V)
ADR421
2.5V REF
NOTE 1
1M⍀
100nF
50k⍀ + CREF
NOTE 2
1F
NOTE 3
50⍀
AVDD
REF
AGND
REFGND
–
NOTE 4 U1
ANALOG INPUT+
+
AD8021
15⍀
CC 2.7nF
NOTE 5
IN+
50⍀
–
NOTE 4 U2
ANALOG INPUT–
+
AD8021
15⍀
CC 2.7nF
NOTE 5
IN–
DGND DVDD OVDD
OGND
SCLK
SDOUT
BUSY
CNVST
AD7676
OB/2C
SER/PAR
SERIAL PORT
50⍀
NOTE 7
D
DVDD
C/P/DSP
CS
RD
BYTESWAP
RESET
PD
CLOCK
NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION.
2. WITH THE RECOMMENDED VOLTAGE REFERENCES, CREF IS 47F. SEE CHAPTER VOLTAGE REFERENCE INPUT SECTION
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
5. SEE ANALOG INPUT SECTION.
6. OPTION, SEE POWER SUPPLY SECTION
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
Figure 5. Typical Connection Diagram. (±2.5 V Range Shown)
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7676.
Different circuitry shown on this diagram are optional and are
discussed below.
Analog Inputs
The AD7676 is specified to operate with a differential ± 2.5 V
range. The typical input impedance for each analog input range
is also shown.
AVDD
cause these diodes to become forward-biased and start conduct-
ing current. These diodes can handle a forward-biased current
of 120 mA maximum. This condition could eventually occur
when the input buffer’s (U1) or (U2) supplies are different
from AVDD. In such case, an input buffer with a short-circuit
current limitation can be used to protect the part.
This analog input structure is a true differential structure. By
using these differential inputs, signals common to both inputs
are rejected as shown in Figure 7 which represents the typical
CMRR over frequency.
R+ = 684⍀
IN+
CS
CS
IN–
R– = 684⍀
AGND
Figure 6. AD7676 Simplified Analog Input
Figure 6 shows a simplified analog input section of the AD7676.
The diodes shown in Figure 6 provide ESD protection for the
inputs. Care must be taken to ensure that the analog input sig-
nal never exceeds the absolute ratings on these inputs. This will
REV. 0
–11–
85
80
75
70
65
60
55
50
45
40
1k
10k 100k 1M
FREQUENCY – Hz
10M
Figure 7. Analog Input CMRR vs. Frequency
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD7676.PDF ] | |
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