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AD7669 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7669
Beschreibung LC2MOS Complete/ 8-Bit Analog I/0 Systems
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD7669 Datasheet, Funktion
a
FEATURES
2 s ADC with Track/Hold
1 s DAC with Output Amplifier
AD7569, Single DAC Output
AD7669, Dual DAC Output
On-Chip Bandgap Reference
Fast Bus Interface
Single or Dual 5 V Supplies
LC2MOS
Complete, 8-Bit Analog I/0 Systems
AD7569/AD7669
AD7569 FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7569/AD7669 is a complete, 8-bit, analog I/O system
on a single monolithic chip. The AD7569 contains a high speed
successive approximation ADC with 2 µs conversion time, a track/
hold with 200 kHz bandwidth, a DAC and an output buffer ampli-
fier with 1 µs settling time. A temperature-compensated 1.25 V
bandgap reference provides a precision reference voltage for the
ADC and the DAC. The AD7669 is similar, but contains two
DACs with output buffer amplifiers.
A choice of analog input/output ranges is available. Using a sup-
ply voltage of +5 V, input and output ranges of zero to 1.25 V
and zero to 2.5 volts may be programmed using the RANGE in-
put pin. Using a ± 5 V supply, bipolar ranges of ± 1.25 V or
± 2.5 V may be programmed.
Digital interfacing is via an 8-bit I/O port and standard micro-
processor control lines. Bus interface timing is extremely fast, al-
lowing easy connection to all popular 8-bit microprocessors. A
separate start convert line controls the track/hold and ADC to
give precise control of the sampling period.
The AD7569/AD7669 is fabricated in Linear-Compatible
CMOS (LC2MOS), an advanced, mixed technology process
combining precision bipolar circuits with low power CMOS
logic. The AD7569 is packaged in a 24-pin, 0.3" wide “skinny”
DIP, a 24-terminal SOIC and 28-terminal PLCC and LCCC
packages. The AD7669 is available in a 28-pin, 0.6" plastic
DIP, 28-terminal SOIC and 28-terminal PLCC package.
AD7669 FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. Complete Analog I/O on a Single Chip.
The AD7569/AD7669 provides everything necessary to
interface a microprocessor to the analog world. No external
components or user trims are required and the overall accu-
racy of the system is tightly specified, eliminating the need
to calculate error budgets from individual component
specifications.
2. Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications,
the AD7569/AD7669 is specified for ac parameters, includ-
ing signal-to-noise ratio, distortion and input bandwidth.
3. Fast Microprocessor Interface.
The AD7569/AD7669 has bus interface timing compatible
with all modern microprocessors, with bus access and relin-
quish times less than 75 ns and write pulse width less than
80 ns.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996






AD7669 Datasheet, Funktion
AD7569/AD7669
DIP, SOIC
AD7569 PIN CONFIGURATIONS
PLCC
LCCC
AD7669 PIN CONFIGURATIONS
DIP, SOIC
PLCC
ORDERING GUIDE
Model
Temperature
Range
Relative
Accuracy
TMIN –TMAX
Package
Option1
AD7569JN
AD7569JR
AD7569AQ
AD7569SQ2
AD7569BN
AD7569KN
AD7569BR
AD7569BQ
AD7569TQ2
AD7569JP
AD7569SE2
AD7569KP
AD7569TE2
AD7669AN
AD7669JN
AD7669JP
AD7669AR
AD7669JR
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 0.5 LSB
± 0.5 LSB
± 0.5 LSB
± 0.5 LSB
± 1/2 LSB
± 1 LSB
± 1 LSB
± 1/2 LSB
± 1/2 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
N-24
R-24
Q-24
Q-24
N-24
N-24
R-24
Q-24
Q-24
P-28A
E-28A
P-28A
E-28A
N-28
N-28
P-28A
R-28
R-28
NOTES
1E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = Small Outline SOIC.
2To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact your local sales office for military data sheet.
–6– REV. B

6 Page









AD7669 pdf, datenblatt
AD7569/AD7669
MODE 1 INTERFACE
The timing diagram for the first mode is shown in Figure 10. It
can be used in digital signal processing and other applications
where precise sampling in time is required. In these applica-
tions, it is important that the signal sampling occurs at exactly
equal intervals to minimize errors due to sampling uncertainty
or jitter. In these cases, the ST line is driven by a timer or some
precise clock source.
The falling edge of the ST pulse starts conversion and drives the
AD7569/AD7669 track-and-hold amplifier into its hold mode.
BUSY stays low for the duration of conversion and returns high
at the end of conversion and the track-and hold amplifier reverts
to its tracking mode on this rising edge of BUSY. The INT line
can be used to interrupt the microprocessor. A READ to the
AD7569/AD7669 address accesses the data, and the INT line is
reset on the rising edge of CS or RD. Alternatively, the INT can
be used to trigger a pulse that drives the CS and RD and places
the data into a FIFO or buffer memory. The microprocessor can
then read a batch of data from the FIFO or buffer memory at
some convenient time. The ST input should not be high when
RD is brought low; otherwise, the part will not operate correctly
in this mode.
It is important, especially in systems where the conversion start
(ST pulse) is asynchronous to the microprocessor, that a READ
does not occur during a conversion. Trying to read data from
the device during a conversion can cause errors to the conver-
sion in progress. Also, pulsing the ST line a second time before
conversion ends should be avoided since it too can cause errors
in the conversion result. In applications where precise sampling
is not critical, the ST pulse can be generated from a micropro-
cessor WR or RD line gated with a decoded address (different
from AD7569/AD7669 CS address).
Figure 11. Multichannel Inputs
This interface mode is also useful in applications where a num-
ber of input channels are required to be converted by the ADC.
Figure 11 shows the circuit configuration for such an applica-
tion. The signal that drives the ST input of the AD7569/
AD7669 is also used to drive the ENABLE input of the multi-
plexer. The multiplexer is enabled on the rising edge of the ST
pulse while the input signal is held on the falling edge; therefore,
the signal must have settled to within 8 bits over the duration of
this ST pulse. The settling time, including tON (ENABLE) of
the multiplexer plus the T/H acquisition time (typically 200 ns),
thus determines the width of the ST pulse. This is suited to ap-
plications where a number of input channels needs to be succes-
sively sampled or scanned.
MODE 2 INTERFACE
The second interface mode is intended for use with micropro-
cessors, which can be forced into a WAIT state for at least 2 µs.
The ST line of the AD7569/AD7669 must be hardwired high to
achieve this mode. The microprocessor starts a conversion and
is halted until the result of the conversion is read from the con-
verter. Conversion is initiated by executing a memory READ to
the AD7569/AD7669 address, bringing CS and RD low. BUSY
subsequently goes low (forcing the microprocessor READY or
WAIT input low), placing the microprocessor into a WAIT
state. The input signal is held on the falling edge of RD (assum-
ing CS is already low or is coincident with RD). When the con-
version is complete (BUSY goes high), the processor completes
the memory READ and acquires the newly converted data.
While conversion is in progress, the ADC places old data (from
the previous conversion) on the data bus. The timing diagram
for this interface is shown in Figure 12.
Figure 12. ADC Mode 2 Interface Timing
The major advantage of this interface is that it allows the micro-
processor to start conversion, WAIT, and then READ data with
a single READ instruction. The user does not have to worry
about servicing interrupts or ensuring that software delays are
long enough to avoid reading during conversion. The fast con-
version time of the ADC ensures that for many microprocessors,
the processor is not placed in a WAIT state for an excessive
amount of time.
DIGITAL SIGNAL PROCESSING APPLICATIONS
In Digital Signal Processing (DSP) application areas such as
voice recognition, echo cancellation and adaptive filtering, the
dynamic characteristics (SNR, Harmonic Distortion, Intermod-
ulation Distortion) of both the ADC and DAC are critical. The
AD7569/AD7669 is specified dynamically as well as with stan-
dard dc specifications. Because the track/hold amplifier has a
wide bandwidth, an antialiasing filter should be placed on the
VIN input to avoid aliasing of high-frequency noise back into the
band of interest.
The dynamic performance of the ADC is evaluated by applying a
sine-wave signal of very low distortion to the VIN input, which is
sampled at a 409.6 kHz sampling rate. A Fast Fourier Transform
(FFT) plot or Histogram plot is then generated from which SNR,
harmonic distortion and dynamic differential nonlinearity data
can be obtained. For the DAC, the codes for an ideal sine wave
are stored in PROM and loaded down to the DAC. The output
spectrum is analyzed, using a spectrum analyzer to evaluate SNR
–12–
REV. B

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