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Teilenummer | AD7660 |
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Beschreibung | 16-Bit/ 100 kSPS CMOS ADC | |
Hersteller | Analog Devices | |
Logo | ||
Gesamt 20 Seiten a
FEATURES
Throughput: 100 kSPS
INL: ؎3 LSB Max (؎0.0046% of Full-Scale)
16 Bits Resolution with No Missing Codes
S/(N+D): 87 dB Min, 90 dB Typ @ 10 kHz
THD: –96 dB Max @ 10 kHz
Analog Input Voltage Range: 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
Single 5 V Supply Operation
21 mW Typical Power Dissipation, 21 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flatpack (LQFP)
Pin-to-Pin Compatible with the AD7664
APPLICATIONS
Data Acquisition
Battery-Powered Systems
PCMCIA
Instrumentation
Automatic Test Equipment
Scanners
Medical Instruments
Process Control
16-Bit, 100 kSPS CMOS ADC
AD7660*
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND REF REFGND
DVDD DGND
IN
INGND
AD7660
SWITCHED
CAP DAC
SERIAL
PORT
16
PD
RESET
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
PARALLEL
INTERFACE
OVDD
OGND
DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
CNVST
GENERAL DESCRIPTION
The AD7660 is a 16-bit, 100 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. The part contains an internal conversion clock, error cor-
rection circuits, and both serial and parallel system interface ports.
The AD7660 is hardware factory calibrated and is comprehensively
tested to ensure such ac parameters as signal-to-noise ratio (SNR)
and total harmonic distortion (THD), in addition to the more
traditional dc parameters of gain, offset, and linearity.
It is fabricated using Analog Devices’ high-performance, 0.6
micron CMOS process with correspondingly low cost, and is
available in a 48-lead LQFP with operation specified from
–40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD7660 is a 100 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Superior INL
The AD7660 has a maximum integral nonlinearity of 3 LSBs
with no missing 16-bit code.
3. Single-Supply Operation
The AD7660 operates from a single 5 V supply and only
dissipates 21 mW typical. Its power dissipation decreases
with the throughput to, for instance, only 21 µW at a 100 SPS
throughput. It consumes 7 µW maximum when in power-down.
4. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement com-
patible with both 3 V or 5 V logic.
*Patent pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD7660
Pin
No. Mnemonic Type
22
DATA[9]
DI/O
or SCLK
23
DATA[10]
DO
or SYNC
24
DATA[11]
DO
or RDERROR
25–28
29
DATA[12:15] DO
BUSY
DO
30 DGND P
31 RD
DI
32 CS
DI
33 RESET DI
34 PD
DI
35
CNVST
DI
36 AGND
37 REF
38 REFGND
39 INGND
43 IN
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
P
AI
AI
AI
AI
Description
When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data Output
Bus.
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output
Bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH
while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High,
SYNC is driven LOW and remains LOW while SDOUT output is valid.
When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used
as an incomplete read error flag. In slave mode, when a data read is started and not complete
when the following conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regard-
less of the state of SER/PAR.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data ready clock signal.
Must be tied to digital ground.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled. RD and CS are OR’d together internally.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled. RD and CS are OR’d together internally.
Reset Input. When set to a logic HIGH, reset the AD7660. Current conversion if any is aborted.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
Start Conversion. If CNVST is HIGH when the acquisition phase (t8) is complete, the next
falling edge on CNVST puts the internal sample/hold into the hold state and initiates a con-
version. This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW
when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state
and a conversion is immediately started.
Must be tied to analog ground.
Reference Input Voltage.
Reference Input Analog Ground.
Analog Input Ground.
Primary analog input with a range of 0 V to VREF.
–6– REV. 0
6 Page AD7660
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7660.
AVDD
IN
OR INGND
AGND
D1
C1
D2
R1 C2
Figure 5. Equivalent Analog Input Circuit
Analog Input
Figure 5 shows an equivalent circuit of the input structure of the
AD7660.
The two diodes D1 and D2 provide ESD protection for the
analog inputs IN and INGND. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 0.3 V. This will cause these diodes to become for-
ward-biased and start conducting current. These diodes can
handle a forward-biased current of 100 mA maximum. For
instance, these conditions could eventually occur when the
input buffer's (U1) supplies are different from AVDD. In such
case, an input buffer with a short circuit current limitation can
be used to protect the part.
This analog input structure allows the sampling of the differen-
tial signal between IN and INGND. Unlike other converters,
the INGND input is sampled at the same time as the IN input.
By using this differential input, small signals common to both
inputs are rejected as shown in Figure 7 which represents the
typical CMR over frequency. For instance, by using INGND to
sense a remote signal ground, difference of ground potentials
between the sensor and the local ADC ground are eliminated.
80
70
60
50
40
30
20
10
0
0.1k
1k 10k 100k 1M
COMMON-MODE INPUT FREQUENCY – Hz
10M
Figure 7. Analog Input CMR vs. Frequency
During the acquisition phase, the impedance of the analog input
IN can be modeled as a parallel combination of capacitor C1
and the network formed by the series connection of R1 and C2.
Capacitor C1 is primarily the pin capacitance. The resistor R1 is
typically 3242 Ω and is a lumped component made up of some
serial resistor and the on resistance of the switches. The capacitor
C2 is typically 60 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to C1. It has to be noted that the
input impedance of the AD7660, unlike other SAR ADCs, is
not a pure capacitance and thus, inherently reduces the kickback
transient at the beginning of the acquisition phase. The R1, C2
makes a one-pole low-pass filter that reduces undesirable
aliasing effect and limits the noise.
ANALOG
SUPPLY
(5V)
2.5V REF1
ANALOG INPUT
(0V TO 2.5V)
10F 100nF
100⍀
10F 100nF
100nF
10F
DIGITAL SUPPLY
(3.3V OR 5V)
AVDD AGND
DGND DVDD OVDD OGND
CREF1
REF
100nF
REFGND
SCLK
SDOUT
U12 IN
AD7660
INGND
PD RESET
BUSY
CNVST
OB/ 2C
SER/ PAR
CS
RD
SERIAL
PORT
D3
DVDD
C/ P/DSP
CLOCK
NOTES:
1WITH THE AD780 OR THE ADR291 VOLTAGE REFERENCE, CREF IS 47F
2THE AD8519 IS RECOMMENDED
3OPTIONAL LOW JITTER CNVST
Figure 6. Typical Connection Diagram
–12–
REV. 0
12 Page | ||
Seiten | Gesamt 20 Seiten | |
PDF Download | [ AD7660 Schematic.PDF ] |
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