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PDF AD7653 Data sheet ( Hoja de datos )
| Número de pieza | AD7653 | |
| Descripción | 16-Bit 1 MSPS SAR Unipolar ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Throughput:
1 MSPS (Warp mode)
800 kSPS (Normal mode)
666 kSPS (Impulse mode)
16-bit resolution
Analog input voltage range: 0 V to 2.5 V
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI®/QSPITM/MICROWIRETM/DSP compatible
Single 5 V supply operation
Power dissipation
92 mW typ @ 666 kSPS, 138 µW @ 1 kSPS without REF
128 mW typ @ 1 MSPS with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs
APPLICATIONS
Data acquisition
Instrumentation
Digital signal processing
Spectrum analysis
Medical instruments
Battery-powered systems
Process control
GENERAL DESCRIPTION
The AD7653 is a 16-bit, 1 MSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed 16-bit sampling
ADC, internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system interface
ports. It features a very high sampling rate mode (Warp), a fast
mode (Normal) for asynchronous conversion rate applications,
and a reduced power mode (Impulse) for low power applica-
tions where power is scaled with the throughput. The AD7653
is fabricated using Analog Devices’ high performance, 0.6
micron CMOS process, with correspondingly low cost. It is
available in a 48-lead LQFP and a tiny 48-lead LFCSP with
operation specified from –40°C to +85°C.
16-Bit 1 MSPS PulSAR
Unipolar ADC with Reference
AD7653
FUNCTIONAL BLOCK DIAGRAM
REFBUFIN REF REFGND
DVDD DGND
AGND
AVDD
IN
INGND
PDREF
PDBUF
PD
RESET
REF
AD7653
SWITCHED
CAP DAC
CLOCK
SERIAL
PORT
16
PARALLEL
INTERFACE
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
WARP IMPULSE CNVST
Figure 1.
OVDD
OGND
DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
BYTESWAP
02966-0-001
Table 1. PulSAR™ Selection
Type/kSPS
Pseudo-
Differential
True Bipolar
True
Differential
18-Bit
Multichannel/
Simultaneous
100–250
AD7651
AD7660/AD7661
AD7663
AD7675
AD7678
500–570
AD7650/AD7652
AD7664/AD7666
AD7666
AD7676
AD7679
AD7654
AD7655
800–
1000
AD7653
AD7667
AD7671
AD7677
AD7674
PRODUCT HIGHTLIGHTS
1. Fast Throughput.
The AD7653 is a 1 MSPS, charge redistribution, 16-bit SAR
ADC with internal error correction circuitry.
2. Internal Reference.
The AD7653 has an internal reference with a typical
temperature drift of 7 ppm/°C.
3. Single-Supply Operation.
The AD7653 operates from a single 5 V supply. In Impulse
mode, its power dissipation decreases with the throughput.
4. Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD7653
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter
Symbol Min
Refer to Figure 26 and Figure 27
Convert Pulse Width
Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1
t1
t2
10
1/1.25/1.5
CNVST LOW to BUSY HIGH Delay
t3
BUSY HIGH All Modes Except Master Serial Read after Convert
(Warp Mode/Normal Mode/Impulse Mode)
t4
Aperture Delay
t5
End of Conversion to BUSY LOW Delay
t6 10
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
t7
Acquisition Time
t8 250
RESET Pulse Width
t9 10
Refer to Figure 28, Figure 29, and Figure 30 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) t10
DATA Valid to BUSY LOW Delay
t11 12
Bus Access Request to DATA Valid
t12
Bus Relinquish Time
t13 5
Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay
t14
CS LOW to Internal SCLK Valid Delay2
t15
CS LOW to SDOUT Delay
t16
CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode)
t17
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period3
Internal SCLK HIGH3
Internal SCLK LOW3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SCLK Last Edge to SYNC Delay3
t18 3
t19 25
t20 12
t21 7
t22 4
t23 2
t24 3
CS HIGH to SYNC HI-Z
t25
CS HIGH to Internal SCLK HI-Z
t26
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert3
t27
(Warp Mode/Normal Mode/Impulse Mode)
t28
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
t29
SYNC Deasserted to BUSY LOW Delay
t30
Refer to Figure 34 and Figure 35 (Slave Serial Interface Modes) 2
External SCLK Setup Time
t31 5
External SCLK Active Edge to SDOUT Delay
t32 3
SDIN Setup Time
t33 5
SDIN Hold Time
t34 5
External SCLK Period
t35 25
External SCLK HIGH
t36 10
External SCLK LOW
t37 10
Typ
2
25/275/525
See Table 4
0.75/1/1.25
25
Max
35
0.75/1/1.25
0.75/1/1.25
0.75/1/1.25
45
15
10
10
10
40
10
10
10
18
Unit
ns
μs
ns
μs
ns
ns
μs
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
1 In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3 In Serial Master Read during Convert Mode. See Table 4 for Serial Master Read after Convert mode.
Rev. B | Page 5 of 28
5 Page 
Data Sheet
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Full-Scale Error
The last transition (from 011…10 to 011…11 in twos
complement coding) should occur for an analog voltage 1½ LSB
below the nominal full scale (2.49994278 V for the 0 V to 2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.
Unipolar Zero Error
The first transition should occur at a level ½ LSB above analog
ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero
error is the deviation of the actual transition from that point.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
AD7653
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the AD7653 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
Overvoltage Recovery
Overvoltage recovery is the time required for the ADC to
recover to full accuracy after an analog input signal 150% of the
full-scale value is reduced to 50% of the full-scale value.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is the change of
internal reference voltage output voltage V over the operating
temperature range and normalized by the output voltage at
25°C, expressed in ppm/°C. The equation follows:
TCV
(
ppm / °C )
=
V(T2) –V(T1)
V(25°C)× (T2 –T1)
×106
where:
V(25°C) = V at +25°C
V(T2) = V at Temperature 2 (+85°C)
V(T1) = V at Temperature 1 (–40°C)
Rev. B | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD7653.PDF ] | |
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