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AD9764 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9764
Beschreibung TxDAC D/A Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 23 Seiten
AD9764 Datasheet, Funktion
a
14-Bit, 125 MSPS
TxDAC® D/A Converter
AD9764
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
14-Bit Resolution
Excellent SFDR and IMD
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 190 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Basestations
ADSL/HFC Modems
Instrumentation
PRODUCT DESCRIPTION
The AD9764 is the 14-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC family, which consists of pin
compatible 8-, 10-, 12-, and 14-bit DACs, is specifically opti-
mized for the transmit signal path of communication systems.
All of the devices share the same interface options, small outline
package and pinout, providing an upward or downward compo-
nent selection path based on performance, resolution and cost.
The AD9764 offers exceptional ac and dc performance while
supporting update rates up to 125 MSPS.
The AD9764’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW with a slight degradation in performance
by lowering the full-scale current output. Also, a power-down
mode reduces the standby power dissipation to approximately
25 mW.
The AD9764 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input
latches and a 1.2 V temperature compensated bandgap refer-
ence have been integrated to provide a complete monolithic
DAC solution. Flexible supply options support +3 V and +5 V
CMOS logic families.
The AD9764 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 koutput impedance.
TxDAC is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
+5V
0.1F
0.1F
RSET
+5V
CLOCK
REFLO
+1.20V REF
REFIO
FS ADJ
COMP1 AVDD ACOM
50pF
AD9764
CURRENT
SOURCE
ARRAY
0.1F
COMP2
DVDD
DCOM
SEGMENTED
SWITCHES
LSB
SWITCHES
IOUTA
IOUTB
CLOCK
SLEEP
LATCHES
DIGITAL DATA INPUTS (DB13–DB0)
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9764 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9764 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9764 may operate
at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9764 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9764 is a member of the TxDAC product family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
2. Manufactured on a CMOS process, the AD9764 uses a pro-
prietary switching technique that enhances dynamic perfor-
mance beyond that previously attainable by higher power/cost
bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches readily interface
to +3 V and +5 V CMOS logic families. The AD9764 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 2.7 V to 5.5 V, and
a wide full-scale current adjustment span of 2 mA to 20 mA,
allows the AD9764 to operate at reduced power levels.
5. The current output(s) of the AD9764 can be easily config-
ured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 World Wide Web Site: http://www.analog.com
Fax:781/326-8703
© Analog Devices, Inc., 1999-2016






AD9764 Datasheet, Funktion
PIN CONFIGURATION
(MSB) DB13 1
28 CLOCK
DB12 2
27 DVDD
DB11 3
26 DCOM
DB10 4
25 NC
DB9 5 AD9764 24 AVDD
DB8 6 TOP VIEW 23 COMP2
DB7 7 (Not to Scale) 22 IOUTA
DB6 8
21 IOUTB
DB5 9
20 ACOM
DB4 10
19 COMP1
DB3 11
18 FS ADJ
DB2 12
17 REFIO
DB1 13
16 REFLO
DB0 14
15 SLEEP
NC = NO CONNECT
AD9764
Pin No.
1
2–13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN FUNCTION DESCRIPTIONS
Name
Description
DB13
Most Significant Data Bit (MSB).
DB12–DB1 Data Bits 1–12.
DB0 Least Significant Data Bit (LSB).
SLEEP
Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if
not used.
REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
FS ADJ Full-Scale Current Output Adjust.
COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.
ACOM Analog Common.
IOUTB
IOUTA
COMP2
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
AVDD
Analog Supply Voltage (+2.7 V to +5.5 V).
NC No Internal Connection.
DCOM Digital Common.
DVDD
Digital Supply Voltage (+2.7 V to +5.5 V).
CLOCK Clock Input. Data latched on positive edge of clock.
REV. C
–5–

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AD9764 pdf, datenblatt
AD9764
AVDD
AVDD
1.2V
AD1580
OPTIONAL
BANDLIMITING
CAPACITOR
REFLO
COMP1 AVDD
RFB
VDD
OUT1
AD7524 VREF
OUT2
AGND
DB7–DB0
0.1V TO 1.2V
RSET
IREF =
VREF/RSET
+1.2V REF
REFIO
FS ADJ
AD9764
50pF
CURRENT
SOURCE
ARRAY
Figure 25. Single-Supply Gain Control Circuit
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed, and IREF is
varied by an external voltage, VGC, applied to RSET via an ampli-
fier. An example of this method is shown in Figure 26 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, VGC, is
referenced to ACOM and should not exceed 1.2 V. The value of
RSET is such that IREFMAX and IREFMIN do not exceed 62.5 µA
and 625 µA, respectively. The associated equations in Figure 26
can be used to determine the value of RSET.
OPTIONAL
BANDLIMITING
CAPACITOR
AVDD
REFLO
COMP1 AVDD
+1.2V REF
50pF
REFIO
CURRENT
1F
FS ADJ
SOURCE
ARRAY
RSET
IREF
AD9764
VGC
IREF = (1.2–VGC)/RSET
WITH VGC < VREFIO AND 62.5A Յ IREF Յ 625A
Figure 26. Dual-Supply Gain Control Circuit
In some applications, the user may elect to use an external
control amplifier to enhance the multiplying bandwidth,
distortion performance and/or settling time. External amplifiers
capable of driving a 50 pF load such as the AD817 are suitable
for this purpose. It is configured in such a way that it is in
parallel with the weaker internal reference amplifier as shown in
Figure 27. In this case, the external amplifier simply overdrives
the weaker reference control amplifier. Also, since the internal
control amplifier has a limited current output, it will sustain no
damage if overdriven.
EXTERNAL
CONTROL AMPLIFIER
VREF
INPUT
RSET
REFLO
+1.2V REF
REFIO
FS ADJ
AD9764
AVDD
COMP1 AVDD
50pF
CURRENT
SOURCE
ARRAY
Figure 27. Configuring an External Reference Control
Amplifier
ANALOG OUTPUTS
The AD9764 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end
or differential operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, VOUTA and
VOUTB, via a load resistor, RLOAD, as described in the DAC
Transfer Function section by Equations 5 through 8. The
differential voltage, VDIFF, existing between VOUTA and VOUTB
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 28 shows the equivalent analog output circuit of the
AD9764 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
and is typically 100 kin parallel with 5 pF. Due to the na-
ture of a PMOS device, the output impedance is also slightly
dependent on the output voltage (i.e., VOUTA and VOUTB) and, to
a lesser extent, the analog supply voltage, AVDD, and full-scale
current, IOUTFS. Although the output impedance’s signal depen-
dency can be a source of dc nonlinearity and ac linearity (i.e.,
distortion), its effects can be limited if certain precautions are
noted.
AD9764
AVDD
IOUTA
RLOAD
IOUTB
RLOAD
Figure 28. Equivalent Analog Output Circuit
IOUTA and IOUTB also have a negative and positive voltage compli-
ance range. The negative output compliance range of –1.0 V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
output stage and affect the reliability of the AD9764. The posi-
tive output compliance range is slightly dependent on the full-
scale output current, IOUTFS. It degrades slightly from its nominal
REV. C
–11–

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