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PDF AD9763 Data sheet ( Hoja de datos )
| Número de pieza | AD9763 | |
| Descripción | Dual TxDAC+ Digital-to-Analog Converters | |
| Fabricantes | Analog Devices | |
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Data Sheet
10-/12-/14-Bit, 125 MSPS
Dual TxDAC+ Digital-to-Analog Converters
AD9763/AD9765/AD9767
FEATURES
10-/12-/14-bit dual transmit digital-to-analog converters (DACs)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single-resistor gain control
Dual-port or interleaved data
On-chip 1.2 V reference
5 V or 3.3 V operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
APPLICATIONS
Communications
Base stations
Digital synthesis
Quadrature modulation
3D ultrasound
GENERAL DESCRIPTION
The AD9763/AD9765/AD9767 are dual-port, high speed,
2-channel, 10-/12-/14-bit CMOS DACs. Each part integrates
two high quality TxDAC+® cores, a voltage reference, and digital
interface circuitry into a small 48-lead LQFP. The AD9763/
AD9765/AD9767 offer exceptional ac and dc performance
while supporting update rates of up to 125 MSPS.
The AD9763/AD9765/AD9767 have been optimized for
processing I and Q data in communications applications. The
digital interface consists of two double-buffered latches as well
as control logic. Separate write inputs allow data to be written to
the two DAC ports independent of one another. Separate clocks
control the update rate of the DACs.
A mode control pin allows the AD9763/AD9765/AD9767 to
interface to two separate data ports, or to a single interleaved
high speed data port. In interleaving mode, the input data
stream is demuxed into its original I and Q data and then
latched. The I and Q data is then converted by the two DACs
and updated at half the input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set
independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor. See the
Gain Control Mode section for important date code
information on this feature.
FUNCTIONAL BLOCK DIAGRAM
DVDD1/ DCOM1/
DVDD2 DCOM2 AVDD ACOM CLK1
PORT1
WRT1/IQWRT
WRT2/IQSEL
PORT2
1
LATCH
1
DAC
DIGITAL
INTERFACE
AD9763/
AD9765/
AD9767
REFERENCE
BIAS
GENERATOR
2
LATCH
2
DAC
IOUTA1
IOUTB1
REFIO
FSADJ1
FSADJ2
GAINCTRL
SLEEP
IOUTA2
IOUTB2
MODE
CLK2/IQ RESET
Figure 1.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
glitch energy and maximize dynamic accuracy. Each DAC provides
differential current output, thus supporting single-ended or dif-
ferential applications. Both DACs of the AD9763, AD9765, or
AD9767 can be simultaneously updated and can provide a
nominal full-scale current of 20 mA. The full-scale currents
between each DAC are matched to within 0.1%.
The AD9763/AD9765/AD9767 are manufactured on an
advanced, low cost CMOS process. They operate from a single
supply of 3.3 V to 5 V and consume 380 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9763/AD9765/AD9767 are members of a pin-
compatible family of dual TxDACs providing 8-, 10-, 12-,
and 14-bit resolution.
2. Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high
performance DACs for each part is optimized for low
distortion performance and provides flexible transmission
of I and Q information.
3. Matching. Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
4. Low Power. Complete CMOS dual DAC function operates on
380 mW from a 3.3 V to 5 V single supply. The DAC full-scale
current can be reduced for lower power operation, and a sleep
mode is provided for low power idle periods.
5. On-Chip Voltage Reference. The AD9763/AD9765/AD9767
each include a 1.20 V temperature-compensated band gap
voltage reference.
6. Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767
each feature a flexible dual-port interface, allowing dual or
interleaved input data.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1999-2011 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
AD9763/AD9765/AD9767
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY1
Integral Linearity Error (INL)
TA = 25°C
TMIN to TMAX
Differential Nonlinearity (DNL)
TA = 25°C
TMIN to TMAX
ANALOG OUTPUT
Offset Error
Gain Error Without Internal Reference
Gain Error with Internal Reference
Gain Match
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small-Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift Without Internal Reference
Gain Drift with Internal Reference
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD1, DVDD2
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)4
Digital Supply Current (IDVDD)5
Supply Current Sleep Mode (IAVDD)
Power Dissipation4 (5 V, IOUTFS = 20 mA)
Power Dissipation5 (5 V, IOUTFS = 20 mA)
Power Dissipation6 (5 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio7—AVDD
Power Supply Rejection Ratio7—DVDD
OPERATING RANGE
AD9763
Min Typ Max
10
AD9765
Min Typ Max
12
AD9767
Min Typ Max
14
Unit
Bits
−1 ±0.1 +1
LSB
−1.5 ±0.4 +1.5 −3.5 ±1.5 +3.5 LSB
−2.0 +2.0 −4.0 +4.0 LSB
LSB
−0.5 ±0.07 +0.5 −0.75 ±0.3 +0.75 −2.5 ±1.0 +2.5 LSB
−1.0 +1.0 −3.0 +3.0 LSB
−0.02
−2
−5
−1.6
−0.14
2.0
−1.0
±0.25
±1
±0.1
100
5
+0.02
+2
+5
+1.6
+0.14
20.0
+1.25
−0.02
−2
−5
−1.6
−0.14
2.0
−1.0
±0.25
±1
±0.1
100
5
+0.02
+2
+5
+1.6
+0.14
20.0
+1.25
−0.02
−2
−5
−1.6
−0.14
2.0
−1.0
±0.25
±1
±0.1
100
5
+0.02
+2
+5
+1.6
+0.14
20.0
+1.25
% of FSR
% of FSR
% of FSR
% of FSR
dB
mA
V
kΩ
pF
1.14 1.20 1.26 1.14 1.20 1.26 1.14 1.20 1.26 V
100 100 100 nA
0.1 1.25 0.1 1.25 0.1 1.25 V
1 1 1 MΩ
0.5 0.5 0.5 MHz
0
±50
±100
±50
0
±50
±100
±50
0
±50
±100
±50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
35
2.7 5
71
5
–0.4
–0.025
–40
8
380
420
450
5.5
5.5
75
7
15
12.0
410
450
+0.4
+0.025
+85
3
2.7
–0.4
–0.025
–40
5
5
71
5
8
380
420
450
5.5
5.5
75
7
15
12.0
410
450
+0.4
+0.025
+85
3
2.7
–0.4
–0.025
–40
5
5
71
5
8
380
420
450
5.5
5.5
75
7
15
12.0
410
450
+0.4
+0.025
+85
V
V
mA
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
°C
1 Measured at IOUTA, driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32 times the IREF current.
3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4 Measured at fCLK = 25 MSPS and fOUT = 1.0 MHz.
5 Measured at fCLK = 100 MSPS and fOUT = 1 MHz.
6 Measured as unbuffered voltage output with IOUTFS = 20 mA and RLOAD = 50 Ω at IOUTA and IOUTB, fCLK = 100 MSPS, and fOUT = 40 MHz.
7 ±10% power supply variation.
Rev. G | Page 5 of 44
5 Page 
Data Sheet
AD9763/AD9765/AD9767
TYPICAL PERFORMANCE CHARACTERISTICS
AD9763
AVDD = 3.3 V or 5 V, DVDD = 3.3 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist,
unless otherwise noted.
90
80
fCLK = 5MSPS
80
0dBFS
75
70
–6dBFS
fCLK = 25MSPS
70
–12dBFS
65
fCLK = 65MSPS
60
50
1
10
fOUT (MHz)
fCLK = 125MSPS
100
Figure 6. SFDR vs. fOUT @ 0 dBFS
60
55
50
0 5 10 15 20 25 30 35
fOUT (MHz)
Figure 9. SFDR vs. fOUT @ 65 MSPS
80
0dBFS
–6dBFS
75
70
–12dBFS
65
0
0.5 1.0 1.5 2.0 2.5
fOUT (MHz)
Figure 7. SFDR vs. fOUT @ 5 MSPS
80
0dBFS
75
70
65
–12dBFS
60
–6dBFS
55
50
0 10 20 30 40 50 60 70
fOUT (MHz)
Figure 10. SFDR vs. fOUT @ 125 MSPS
80
0dBFS
75
70
–12dBFS
65
–6dBFS
80
IOUTFS = 20mA
75
70
65
IOUTFS = 10mA
60
IOUTFS = 5mA
55
60
0 2 4 6 8 10 12
fOUT (MHz)
Figure 8. SFDR vs. fOUT @ 25 MSPS
50
0
5 10 15 20 25 30 35
fOUT (MHz)
Figure 11. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
Rev. G | Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9763.PDF ] | |
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