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AD9761 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9761
Beschreibung Dual 10-Bit TxDAC+
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
AD9761 Datasheet, Funktion
Dual 10-Bit TxDAC+®
with 2Interpolation Filters
AD9761
FEATURES
Complete 10-Bit, 40 MSPS Dual Transmit DAC
Excellent Gain and Offset Matching
Differential Nonlinearity Error: 0.5 LSB
Effective Number of Bits: 9.5
Signal-to-Noise and Distortion Ratio: 59 dB
Spurious-Free Dynamic Range: 71 dB
2Interpolation Filters
20 MSPS/Channel Data Rate
Single Supply: 3 V to 5.5 V
Low Power Dissipation: 93 mW (3 V Supply @
40 MSPS)
On-Chip Reference
28-Lead SSOP
PRODUCT DESCRIPTION
The AD9761 is a complete dual-channel, high speed, 10-bit
CMOS DAC. The AD9761 has been developed specifically for
use in wide bandwidth communication applications (e.g., spread
spectrum) where digital I and Q information is being processed
during transmit operations. It integrates two 10-bit, 40 MSPS
DACs, dual 2interpolation filters, a voltage reference, and digi-
tal input interface circuitry. The AD9761 supports a 20 MSPS
per channel input data rate that is then interpolated by 2up to
40 MSPS before simultaneously updating each DAC.
The interleaved I and Q input data stream is presented to the
digital interface circuitry, which consists of I and Q latches as
well as some additional control logic. The data is de-interleaved
back into its original I and Q data. An on-chip state machine
ensures the proper pairing of I and Q data. The data output from
each latch is then processed by a 2digital interpolation filter
that eases the reconstruction filter requirements. The interpo-
lated output of each filter serves as the input of their respective
10-bit DAC.
The DACs utilize a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and to maximize dynamic accuracy. Each DAC provides
differential current output, thus supporting single-ended or dif-
ferential applications. Both DACs are simultaneously updated
and provide a nominal full-scale current of 10 mA. Also, the
full-scale currents between each DAC are matched to within
0.07 dB (i.e., 0.75%), thus eliminating the need for additional
gain calibration circuitry.
The AD9761 is manufactured on an advanced low cost CMOS
process. It operates from a single supply of 3 V to 5.5 V and
consumes 200 mW of power. To make the AD9761 complete, it
also offers an internal 1.20 V temperature-compensated band gap
reference.
FUNCTIONAL BLOCK DIAGRAM
DCOM DVDD CLOCK ACOM AVDD
SLEEP
DAC DATA
INPUTS
(10 BITS)
WRITE INPUT
SELECT INPUT
LATCH
I
2
I
DAC
REFERENCE
LATCH
Q
MUX
CONTROL
BIAS
GENERATOR
2
Q
DAC
AD9761
IOUTA
IOUTB
REFLO
FSADJ
REFIO
COMP1
COMP2
COMP3
QOUTA
QOUTB
PRODUCT HIGHLIGHTS
1. Dual 10-Bit, 40 MSPS DACs
A pair of high performance 40 MSPS DACs optimized for low
distortion performance provide for flexible transmission of I
and Q information.
2. 2Digital Interpolation Filters
Dual matching FIR interpolation filters with 62.5 dB stop-
band rejection precede each DAC input, thus reducing the
DACs’ reconstruction filter requirements.
3. Low Power
Complete CMOS dual DAC function operates on a low
200 mW on a single supply from 3 V to 5.5 V. The DAC
full-scale current can be reduced for lower power opera-
tion, and a sleep mode is provided for power reduction
during idle periods.
4. On-Chip Voltage Reference
The AD9761 includes a 1.20 V temperature-compensated
band gap voltage reference.
5. Single 10-Bit Digital Input Bus
The AD9761 features a flexible digital interface that allows
each DAC to be addressed in a variety of ways including dif-
ferent update rates.
6. Small Package
The AD9761 offers the complete integrated function in a
compact 28-lead SSOP package.
7. Product Family
The AD9761 Dual Transmit DAC has a pair of Dual Receive
ADC companion products, the AD9281 (8 bits) and AD9201
(10 bits).
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.






AD9761 Datasheet, Funktion
AD9761
ORDERING GUIDE
Model
Package
Description
Package
Option
AD9761ARS 28-Lead Shrink Small Outline (SSOP) RS-28
AD9761ARSRL 28-Lead Shrink Small Outline (SSOP) RS-28
AD9761-EB Evaluation Board
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead SSOP
qJA = 109°C/W
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect to
AVDD
DVDD
ACOM
AVDD
CLOCK, WRITE
SELECT, SLEEP
Digital Inputs
IOUTA, IOUTB
QOUTA, QOUTB
COMP1, COMP2
COMP3
REFIO, FSADJ
REFLO
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
DCOM
ACOM
ACOM
ACOM
ACOM
ACOM
ACOM
Min
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–0.3
–1.0
–1.0
–0.3
–0.3
–0.3
–0.3
–65
Max
+6.5
+6.5
+0.3
+6.5
DVDD + 0.3
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+0.3
150
+150
300
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
2.7V TO
5.5V
3V TO
5.5V
0.1F
0.1F 0.1F
TEKTRONIX
AWG-2021
DIGITAL
DATA
CLOCK
OUT MARKER 1
RETIMED
CLOCK
OUTPUT*
DVDD DCOM COMP2 AVDD AVSS COMP1 COMP3
LATCH
I
2x
I
DAC
IOUTA
IOUTB
REFLO
DB9–DB0
AD9761
REFIO
FSADJ
SELECT
WRITE
CLOCK
LATCH
Q
MUX
CONTROL
2x
SLEEP
Q
DAC
QOUTA
QOUTB
0.1F
RSET
2k
MINI-CIRCUITS
T1-1T
100
5020pF 5020pF
MINI-CIRCUITS
T1-1T
100
5020pF 5020pF
TO HP3589A
SPECTRUM/NETWORK
ANALYZER
50INPUT
TO HP3589A
SPECTRUM/NETWORK
ANALYZER
50INPUT
LE CROY 9210
PULSE GENERATOR
*AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.
Figure 3. Basic AC CharacterizationTest Setup
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9761 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. C
–5–

6 Page









AD9761 pdf, datenblatt
AD9761
log filter is typically determined by the proximity of the desired
fundamental to the first image and the required amount of image
suppression.
Referring to Figure 5, the “new” first image associated with the
DAC’s higher data rate after interpolation is “pushed” out fur-
ther relative to the input signal. The “old” first image associated
with the lower DAC data rate before interpolation is suppressed
by the digital filter. As a result, the transition band for the analog
reconstruction filter is increased, thus reducing the complexity
of the analog filter.
The digital interpolation filters for I and Q paths are identi-
cal 43-tap half-band symmetric FIR filters. Each filter receives
de-interleaved I or Q data from the digital input interface. The
input CLOCK signal is internally divided by 2 to generate the
filter clock. The filters are implemented with two parallel paths
running at the filter clock rate. The output from each path is
selected on opposite phases of the filter clock, thus producing
interpolated filtered output data at the input clock rate. The
frequency response and impulse response of these filters are
shown in Figures 2a and 2b. Table I lists the idealized filter
coefficients that correspond to the filter’s impulse response.
The digital section of the AD9761 also includes an input interface
section designed to support interleaved I and Q input data from
a single 10-bit bus. This section de-interleaves the I and Q input
data while ensuring its proper pairing for the 2interpolation
filters. A RESET/SLEEP input serves a dual function by providing
a reset function for this section as well as providing power-down
functionality. Refer to the Digital Inputs and Interleaved Interface
Considerations and RESET/SLEEP Mode Operation sections for
a more detailed discussion.
DAC TRANSFER FUNCTION
Each I and Q DAC provides complementary current output
pins: IOUT(A/B) and QOUT(A/B), respectively. Note that
QOUTA and QOUTB operate identically to IOUTA and
IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 1023), while
IOUTB, the complementary output, provides no current. The
current outputs of IOUTA and IOUTB are a function of both
the input code and IOUTFS and can be expressed as
( )IOUTA = DAC CODE/1024 × IOUTFS
(1)
( )IOUTB = 1023 – DAC CODE /1024 × IOUTFS
where:
(2)
DAC CODE = 0 to 1023 (i.e., decimal representation).
As previously mentioned, IOUTFS is a function of the reference
current, IREF, which is nominally set by a reference, VREFIO, and
external resistor, RSET. It can be expressed as
IOUTFS = 16 × IREF
(3)
where:
IREF = VREFIO /RSET
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, which are tied to analog common, ACOM. Note
that RLOAD represents the equivalent load resistance seen by
IOUTA or IOUTB. The single-ended voltage output appearing
at IOUTA and IOUTB pins is simply
VIOUTA = IOUTA × RLOAD
(5)
VIOUTB = IOUTB × RLOAD
(6)
Note that the full-scale value of VIOUTA and VIOUTB should not
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
The differential voltage, VIDIFF, appearing across IOUTA and
IOUTB is
( )VIDIFF = IIOUTA IIOUTB × RLOAD
(7)
Substituting the values of IIOUTA, IIOUTB, and IREF, VIDIFF can be
expressed as
{ }VIDIFF = (2 DAC CODE – 1023)/1024) ×
( )16 RLOAD /RSET × VREFIO
(8)
These last two equations highlight some of the advantages of
operating the AD9761 differentially. First, differential opera-
tion will help cancel common-mode error sources associated
with IIOUTA and IIOUTB, such as noise and distortion. Second,
the differential code-dependent current and subsequent volt-
age, VIDIFF, is twice the value of the single-ended voltage output
(i.e., VIOUTA or VIOUTB), thus providing twice the signal power to
the load.
REFERENCE OPERATION
The AD9761 contains an internal 1.20 V band gap reference that
can be easily disabled and overridden by an external reference.
REFIO serves as either an input or output depending on whether
the internal or an external reference is selected. If REFLO is tied
to ACOM as shown in Figure 6, the internal reference is activated
and REFIO provides a 1.20 V output. In this case, the internal ref-
erence must be filtered externally with a ceramic chip capacitor of
0.1 µF or greater from REFIO to REFLO. Also, REFIO should be
buffered with an external amplifier having a low input bias current
(i.e., <1 µA) if any additional loading is required.
OPTIONAL EXTERNAL
REF BUFFER FOR
ADDITIONAL LOADS
REFLO
COMPENSATION
CAPACITOR
REQUIRED
0.1F
RSET
2k
+1.2V REF
REFIO
FSADJ
AD9761
0.1F
COMP2
50pF
AVDD
CURRENT
SOURCE
ARRAY
Figure 6. Internal Reference Configuration
The internal reference can also be disabled by connecting
REFLO to AVDD. In this case, an external reference may then
be applied to REFIO as shown in Figure 7.The external reference
may provide either a fixed reference voltage to enhance accura-
cy and drift performance or a varying reference voltage for gain
control. Note that the 0.1 µF compensation capacitor is not
required since the internal reference is disabled and the high
input impedance (i.e., 1 M) of REFIO minimizes any loading
of the external reference.
REV. C
–11–

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