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PDF AD9760 Data sheet ( Hoja de datos )
| Número de pieza | AD9760 | |
| Descripción | 10-Bit 125 MSPS TxDAC D/A Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
10-Bit, 125 MSPS
TxDAC® D/A Converter
AD9760
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
10-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 40 MHz Output: 52 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Basestations
Set Top Boxes
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9760 and AD9760-50 are the 10-bit resolution members
of the TxDAC series of high performance, low power CMOS
digital-to-analog converters (DACs). The AD9760-50 is a lower
performance option that is guaranteed and specified for 50 MSPS
operation. The TxDAC family that consists of pin compatible 8-,
10-, 12- and 14-bit DACs is specifically optimized for the trans-
mit signal path of communication systems. All of the devices
share the same interface options, small outline package and
pinout, thus providing an upward or downward component
selection path based on performance, resolution and cost. Both
the AD9760 and AD9760-50 offer exceptional ac and dc
performance while supporting update rates up to 125 MSPS
and 60 MSPS respectively.
The AD9760’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.
The AD9760 is manufactured on an advanced CMOS process. A
segmented current source architecture is combined with a propri-
etary switching technique to reduce spurious components and
enhance dynamic performance. Edge-triggered input latches and a
1.2 V temperature compensated bandgap reference have been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
+5V
0.1F
0.1F
RSET +5V
CLOCK
REFLO
+1.20V REF
REFIO
FS ADJ
COMP1 AVDD ACOM
50pF
AD9760
CURRENT
SOURCE
ARRAY
0.1F
COMP2
DVDD
DCOM
SEGMENTED
SWITCHES
LSB
SWITCHES
IOUTA
IOUTB
CLOCK
SLEEP
LATCHES
DIGITAL DATA INPUTS (DB9–DB0)
The AD9760 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9760 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier that provides a wide
(>10:1) adjustment span allows the AD9760 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9760 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9760 is available in a 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9760 is a member of the TxDAC product family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
2. Manufactured on a CMOS process, the AD9760 uses a pro-
prietary switching technique that enhances dynamic perfor-
mance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches interface readily
to +3 V and +5 V CMOS logic families. The AD9760 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 2.7 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9760 to operate at reduced power levels.
5. The current output(s) of the AD9760 can be easily config-
ured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD9760
DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)
Parameter
Min Typ Max
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
Specification subject to change without notice.
3.5 5
2.1 3
0 1.3
0 0.9
–10 +10
–10 +10
5
2.0
1.5
3.5
Units
V
V
V
V
µA
µA
pF
ns
ns
ns
DB0–DB9
CLOCK
IOUTA OR
IOUTB
tS tH
tLPW
tPD tST
0.1%
0.1%
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect to Min
Max
Units
AVDD
DVDD
ACOM
AVDD
CLOCK, SLEEP
Digital Inputs
IOUTA, IOUTB
COMP1, COMP2
REFIO, FSADJ
REFLO
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
ACOM
ACOM
–0.3 +6.5
V
–0.3 +6.5
V
–0.3 +0.3
V
–6.5 +6.5
V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–1.0 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.3 +0.3
V
+150
°C
–65 +150
°C
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
ORDERING GUIDE
Model
Temperature
Range
Package
Package
Descriptions Options
AD9760AR
AD9760ARU
AD9760AR50
AD9760ARU50
AD9760-EB
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Evaluation Board
28-Lead 300 mil R-28
SOIC
28-Lead 170 mil RU-28
TSSOP
28-Lead 300 mil R-28
SOIC
28-Lead 170 mil RU-28
TSSOP
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil (7.5 mm) SOIC
θJA = 71.4°C/W
θJC = 23°C/W
28-Lead 170 mil (4.4 mm) TSSOP
θJA = 97.9°C/W
θJC = 14.0°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9760 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. B
5 Page 
AD9760
–70
–75
2ND
HARMONIC
–80
–85
3RD
HARMONIC
–90
–95
0
4TH
HARMONIC
20 40 60 80 100 120 140
FREQUENCY – MSPS
Figure 30. THD vs. fCLOCK
fOUT = 2 MHz
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0 125 250 375 500 625 750 875 1000
CODE
Figure 33. Typical INL
80
2.5MHz
75
70
10MHz
65
60 22.4MHz
55
28.6MHz
50
45
40
246
8 10 12 14 16 18 20
IREF – mA
Figure 31. SFDR vs. fOUT and IOUTFS
@ 100 MSPS, 0 dBFS
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
0 125 250 375 500 625 750 875 1000
CODE
Figure 34. Typical DNL
75
IOUTA @
70 –6dBFS
IDIFF @
65 –6dBFS
60 IDIFF @
0dBFS
55
50
IOUTA @
0dBFS
45
1 10 100
OUTPUT FREQUENCY – MHz
Figure 32. Differential vs. Single
Ended SFDR vs. fOUT @ 100 MSPS
80
75
70
65
10MHz
60
28.6MHz
55
2.5MHz
50
45
40
–40 –20 0
20 40 60
TEMPERATURE – ؇C
80
Figure 35. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS
0 0 –10
fCLOCK = 125MSPS
fOUT = 9.95MHz
SFDR = 62dBc
AMPLITUDE = 0dBFS
fCLOCK = 100MSPS
fOUT1 = 13.5MHz
fOUT2 = 14.5MHz
SFDR = 59.0dBc
AMPLITUDE = 0dBFS
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
SFDR = 71dBc
AMPLITUDE = 0dBFS
–100
START: 0.3MHz
STOP: 62.5MHz
Figure 36. Single-Tone SFDR
–100
START: 0.3MHz
STOP: 50.0MHz
Figure 37. Dual-Tone SFDR
–110
START: 0.3MHz
STOP: 25.0MHz
Figure 38. Four-Tone SFDR
–10–
REV. B
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD9760.PDF ] | |
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