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AD9753 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9753
Beschreibung 12-Bit 300 MSPS High-Speed TxDAC+ D/A Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 29 Seiten
AD9753 Datasheet, Funktion
FEATURES
12-Bit Dual Muxed Port DAC
300 MSPS Output Update Rate
Excellent SFDR and IMD Performance
SFDR to Nyquist @ 25 MHz Output: 69 dB
Internal Clock Doubling PLL
Differential or Single-Ended Clock Input
On-Chip 1.2 V Reference
Single 3.3 V Supply Operation
Power Dissipation: 155 mW @ 3.3 V
48-Lead LQFP
APPLICATIONS
Communications: LMDS, LMCS, MMDS
Base Stations
Digital Synthesis
QAM and OFDM
12-Bit, 300 MSPS
High Speed TxDAC+®D/A Converter
AD9753*
FUNCTIONAL BLOCK DIAGRAM
DVDD DCOM
AVDD ACOM
PORT1
LATCH
PORT2
LATCH
MUX
DAC
IOUTA
IOUTB
CLK+
CLK–
CLKVDD
PLLVDD
CLKCOM
PLL
CLOCK
MULTIPLIER
REFERENCE
AD9753
RESET LPF DIV0 DIV1 PLLLOCK
REFIO
FSADJ
GENERAL DESCRIPTION
The AD9753 is a dual, muxed port, ultrahigh speed, single-
channel, 12-bit CMOS DAC. It integrates a high quality 12-bit
TxDAC+ core, a voltage reference, and digital interface circuitry
into a small 48-lead LQFP package. The AD9753 offers excep-
tional ac and dc performance while supporting update rates up
to 300 MSPS.
The AD9753 has been optimized for ultrahigh speed applica-
tions up to 300 MSPS where data rates exceed those possible on
a single data interface port DAC. The digital interface consists
of two buffered latches as well as control logic. These latches
can be time multiplexed to the high speed DAC in several ways.
This PLL drives the DAC latch at twice the speed of the exter-
nally applied clock and is able to interleave the data from the
two input channels. The resulting output data rate is twice that
of the two input channels. With the PLL disabled, an external
2× clock may be supplied and divided by two internally.
The CLK inputs (CLK+/CLK–) can be driven either differen-
tially or single-ended, with a signal swing as low as 1 V p-p.
The DAC utilizes a segmented current source architecture
combined with a proprietary switching technique to reduce
glitch energy and to maximize dynamic accuracy. Differential
current outputs support single-ended or differential applica-
tions. The differential outputs each provide a nominal full-scale
current from 2 mA to 20 mA.
The AD9753 is manufactured on an advanced low cost 0.35 µm
CMOS process. It operates from a single supply of 3.0 V to 3.6 V
and consumes 155 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9753 is a member of a pin compatible family of high
speed TxDAC+s providing 10-, 12-, and 14-bit resolution.
2. Ultrahigh Speed 300 MSPS Conversion Rate.
3. Dual 12-Bit Latched, Multiplexed Input Ports. The AD9753
features a flexible digital interface allowing high speed data
conversion through either a single or dual port input.
4. Low Power. Complete CMOS DAC function operates on
155 mW from a 3.0 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation.
5. On-Chip Voltage Reference. The AD9753 includes a 1.20 V
temperature-compensated band gap voltage reference.
*Protected by U.S. Patent numbers 5450084, 5568145, 5689257, and
5703519.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






AD9753 Datasheet, Funktion
AD9753
ABSOLUTE MAXIMUM RATINGS*
Parameter
With Respect to
Min Max
Unit
AVDD, DVDD, CLKVDD, PLLVDD
AVDD, DVDD, CLKVDD, PLLVDD
ACOM, DCOM, CLKCOM, PLLCOM
REFIO, REFLO, FSADJ
IOUTA, IOUTB
Digital Data Inputs (DB13 to DB0)
CLK+/CLK–, PLLLOCK
DIV0, DIV1, RESET
LPF
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
ACOM, DCOM, CLKCOM, PLLCOM
AVDD, DVDD, CLKVDD, PLLVDD
ACOM, DCOM, CLKCOM, PLLCOM
ACOM
ACOM
DCOM
CLKCOM
CLKCOM
PLLCOM
–0.3
–3.9
–0.3
–0.3
–1.0
–0.3
–0.3
–0.3
–0.3
–65
+3.9
+3.9
+0.3
AVDD + 0.3
AVDD + 0.3
DVDD + 0.3
CLKVDD + 0.3
CLKVDD + 0.3
PLLVDD + 0.3
150
+150
300
V
V
V
V
V
V
V
V
V
°C
°C
°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
PORT 1
DATA IN
PORT 2
INPUT CLK
(PLL ENABLED)
IOUTA OR IOUTB
tS tH
DATA X
DATA Y
t LPW
t PD
DATA X
DATA Y
t PD
Figure 1. I/O Timing
ORDERING GUIDE
Model
Temperature Package
Package
Range
Description Option
AD9753AST –40°C to +85°C 48-Lead LQFP ST-48
AD9753ASTRL –40°C to +85°C 48-Lead LQFP ST-48
AD9753-EB
Evaluation
Board
THERMAL CHARACTERISTIC
Thermal Resistance
48-Lead LQFP
JA = 91°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9753 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. B
–5–

6 Page









AD9753 pdf, datenblatt
AD9753
REFERENCE CONTROL AMPLIFIER
The AD9753 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a voltage-to-current
converter as shown in Figure 4, so that its current output, IREF, is
determined by the ratio of VREFIO and an external resistor, RSET,
as stated in Equation 4. IREF is applied to the segmented current
sources with the proper scaling factor to set IOUTFS, as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between
62.5 µA and 625 µA. The wide adjustment span of IOUTFS
provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9753, which is
proportional to IOUTFS (refer to the Power Dissipation section).
The second benefit relates to the 20 dB adjustment, which is
useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency,
small signal multiplying applications.
PLL CLOCK MULTIPLIER OPERATION
The Phase-Locked Loop (PLL) is intrinsic to the operation of
the AD9753 in that it produces the necessary internally syn-
chronized 2× clock for the edge-triggered latches, multiplexer,
and DAC.
With PLLVDD connected to its supply voltage, the AD9753 is
in PLL mode. Figure 6 shows a functional block diagram of the
AD9753 clock control circuitry with PLL active. The circuitry
consists of a phase detector, charge pump, voltage controlled
oscillator (VCO), input data rate range control, clock logic
circuitry, and control input/outputs. The ÷ 2 logic in the feed-
back loop allows the PLL to generate the 2× clock needed for
the DAC output latch.
CLKVDD
(3.0V TO 3.6V) PLLLOCK
3921.0F
LPF PLLVDD
3.0V TO
3.6V
CLK+
CLK–
DIFFERENTIAL-
TO-
SINGLE-ENDED
AMP
PHASE
DETECTOR
TO INPUT
LATCHES
AD9753
CHARGE
PUMP
VCO
RANGE
CONTROL
(،1, 2, 4, 8)
،2
TO DAC
LATCH
CLKCOM
DIV0
DIV1
Figure 6. Clock Circuitry with PLL Active
Figure 7 defines the input and output timing for the AD9753
with the PLL active. CLK in Figure 7 represents the clock
that is generated external to the AD9753. The input data at
both Ports 1 and 2 is latched on the same CLK rising edge.
CLK may be applied as a single-ended signal by tying CLK– to
midsupply and applying CLK to CLK+, or as a differential
signal applied to CLK+ and CLK–.
RESET has no purpose when using the internal PLL and should
be grounded. When the AD9753 is in PLL mode, PLLLOCK
is the output of the internal phase detector. When locked, the
lock output in this mode will be a Logic 1.
PORT 1
DATA IN
PORT 2
tS tH
DATA X
DATA Y
CLK
IOUTA OR IOUTB
t LPW
t PD
DATA X
DATA Y
1/2 CYCLE + tPD
Figure 7a. DAC Input Timing Requirements with
PLL Active, Single Clock Cycle
PORT 1
DATA IN
PORT 2
DATA W
DATA X
DATA Y
DATA Z
CLK
IOUTA OR IOUTB
XXX
DATA W DATA X
DATA Y DATA Z
Figure 7b. DAC Input Timing Requirements with
PLL Active, Multiple Clock Cycles
Typically, the VCO can generate outputs of 100 MHz to
400 MHz. The range control is used to keep the VCO operating
within its designed range, while allowing input clocks as low as
6.25 MHz. With the PLL active, logic levels at DIV0 and DIV1
determine the divide (prescaler) ratio of the range controller.
Table I gives the frequency range of the input clock for the
different states of DIV0 and DIV1.
Table I. CLK Rates for DIV0, DIV1 Levels with PLL Active
CLK Frequency
50 MHz–150 MHz
25 MHz–100 MHz
12.5 MHz–50 MHz
6.25 MHz–25 MHz
DIV1
0
0
1
1
DIV0
0
1
0
1
Range Controller
÷1
÷2
÷4
÷8
A 392 resistor and 1.0 µF capacitor connected in series from
LPF to PLLVDD are required to optimize the phase noise versus
the settling/acquisition time characteristics of the PLL. To
obtain optimum noise and distortion performance, PLLVDD
should be set to a voltage level similar to DVDD and
CLKVDD.
In general, the best phase noise performance for any PLL range
control setting is achieved with the VCO operating near its maxi-
mum output frequency of 400 MHz.
As stated earlier, applications requiring input data rates below
6.25 MSPS must disable the PLL clock multiplier and provide
an external 2× reference clock. At higher data rates however,
applications already containing a low phase noise (i.e., jitter)
REV. B
–11–

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