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PDF AD9740 Data sheet ( Hoja de datos )
| Número de pieza | AD9740 | |
| Descripción | TxDAC D/A Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9740 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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10-Bit, 210 MSPS TxDAC® D/A Converter
AD9740
FEATURES
High performance member of pin-compatible
TxDAC product family
Excellent spurious-free dynamic range performance
SNR @ 5 MHz output, 125 MSPS: 65 dB
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.2 V Reference
CMOS-compatible digital interface
28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP
packages
Edge-triggered latches
GENERAL DESCRIPTION
The AD97401 is a 10-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC
family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit
DACs, is specifically optimized for the transmit signal path
of communication systems. All of the devices share the same
interface options, small outline package, and pinout, providing
an upward or downward component selection path based
on performance, resolution, and cost. The AD9740 offers
exceptional ac and dc performance while supporting update
rates up to 210 MSPS.
The AD9740’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation
can be further reduced to 60 mW with a slight degradation in
performance by lowering the full-scale current output. In
addition, a power-down mode reduces the standby power
dissipation to approximately 15 mW. A segmented current
source architecture is combined with a proprietary switching
technique to reduce spurious components and enhance
dynamic performance.
APPLICATIONS
Wideband communication transmit channel
Direct IF
Base stations
Wireless local loops
Digital radio links
Direct digital synthesis (DDS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3V
0.1μF
RSET 3.3V
CLOCK
REFLO
1.2V REF
REFIO
FS ADJ
150pF
AVDD ACOM
CURRENT AD9740
SOURCE
ARRAY
DVDD
DCOM
SEGMENTED
SWITCHES
LSB
SWITCHES
IOUTA
IOUTB
CLOCK
LATCHES
MODE
SLEEP
DIGITAL DATA INPUTS (DB9–DB0)
Figure 1.
Edge-triggered input latches and a 1.2 V temperature-compensated
band gap reference have been integrated to provide a complete
monolithic DAC solution. The digital inputs support 3 V CMOS
logic families.
PRODUCT HIGHLIGHTS
1. The AD9740 is the 10-bit member of the pin-compatible
TxDAC family, which offers excellent INL and DNL
performance.
2. Data input supports twos complement or straight binary
data coding.
3. High speed, single-ended CMOS clock input supports
210 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
5. On-chip voltage reference: The AD9740 includes a 1.2 V
temperature-compensated band gap voltage reference.
6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-
lead LFCSP packages.
1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD9740
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (External Reference)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
CLKVDD
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)4
Clock Supply Current (ICLKVDD)
Supply Current Sleep Mode (IAVDD)
Power Dissipation4
Power Dissipation5
Power Supply Rejection Ratio—AVDD6
Power Supply Rejection Ratio—DVDD6
OPERATING RANGE
Min
10
−0.7
−0.5
−0.02
−2
−2
2
−1
1.14
0.1
Typ
±0.15
±0.12
±0.1
±0.1
100
5
1.20
100
7
0.5
0
±50
±100
±50
Max
+0.7
+0.5
+0.02
+2
+2
20
+1.25
1.26
1.25
2.7
2.7
2.7
−1
−0.04
−40
3.3
3.3
3.3
33
8
5
5
135
145
3.6
3.6
3.6
36
9
6
6
145
+1
+0.04
+85
1 Measured at IOUTA, driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32 times the IREF current.
3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4 Measured at fCLOCK = 25 MSPS and fOUT = 1 MHz.
5 Measured as unbuffered voltage output with IOUTFS = 20 mA, 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS, and fOUT = 40 MHz.
6 ±5% power supply variation.
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
nA
V
kΩ
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
V
V
V
mA
mA
mA
mA
mW
mW
% of FSR/V
% of FSR/V
°C
Rev. B | Page 4 of 32
5 Page 
AD9740
TYPICAL PERFORMANCE CHARACTERISTICS
95
90 125MSPS
210MSPS (LFCSP)
85
165MSPS (LFCSP)
80
75
65MSPS
70
125MSPS (LFCSP)
65
60 210MSPS
55
165MSPS
50
45
0 10 100
fOUT (MHz)
Figure 6. SFDR vs. fOUT @ 0 dBFS
95
90
85
80 0dBFS
75
70 –6dBFS
65 –12dBFS
60
55
50
45
0 5 10 15 20 25
fOUT (MHz)
Figure 7. SFDR vs. fOUT @ 65 MSPS
95
90
0dBFS
85
80
75
70
–12dBFS
65
60
55
–6dBFS
50
45
0 5 10 15 20 25 30 35 40 45
fOUT (MHz)
Figure 8. SFDR vs. fOUT @ 125 MSPS
95
90
0dBFS
85
80
75
–6dBFS
70
65
–12dBFS
60
55
50
45
0 10 20 30 40 50 60
fOUT (MHz)
Figure 9. SFDR vs. fOUT @ 165 MSPS
95
90
85
80
75 20mA
10mA
70
65 5mA
60
55
50
45
0 5 10 15 20
fOUT (MHz)
Figure 10. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
25
95
90
0dBFS (LFCSP)
85
–12dBFS (LFCSP)
80
75 –6dBFS (LFCSP)
70
0dBFS
65
60
–12dBFS
55 –6dBFS
50
45
0 10 20 30 40 50 60 70 80
fOUT (MHz)
Figure 11. SFDR vs. fOUT @ 210 MSPS
Rev. B | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9740.PDF ] | |
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