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AD974 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD974
Beschreibung 4-Channel/ 16-Bit/ 200 kSPS Data Acquisition System
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD974 Datasheet, Funktion
a
4-Channel, 16-Bit, 200 kSPS
Data Acquisition System
AD974
FEATURES
Fast 16-Bit ADC with 200 kSPS Throughput
Four Single-Ended Analog Input Channels
Single +5 V Supply Operation
Input Ranges: 0 V to +4 V, 0 V to +5 V and ؎10 V
120 mW Max Power Dissipation
Power-Down Mode 50 W
Choice of External or Internal 2.5 V Reference
On-Chip Clock
Power-Down Mode
GENERAL DESCRIPTION
The AD974 is a four-channel, data acquisition system with a
serial interface. The part contains an input multiplexer, a high-
speed 16-bit sampling ADC and a +2.5 V reference. All of this
operates from a single +5 V power supply that also has a power-
down mode. The part will accommodate 0 V to +4 V, 0 V to
+5 V or ± 10 V analog input ranges.
The interface is designed for an efficient transfer of data while
requiring a low number of interconnects.
The AD974 is comprehensively tested for ac parameters such as
SNR and THD, as well as the more traditional parameters of
offset, gain and linearity.
The AD974 is fabricated on Analog Devices’ BiCMOS process,
which has high performance bipolar devices along with CMOS
transistors.
The AD974 is available in 28-lead DIP, SOIC and SSOP
packages.
FUNCTIONAL BLOCK DIAGRAM
PWRD
BIP CAP
REF VDIG VANA
V1A
V1B
V2A
V2B
V3A
V3B
V4A
V4B
RESISTIVE
NETWORK
RESISTIVE
NETWORK
RESISTIVE
NETWORK
RESISTIVE
NETWORK
4 TO 1
MUX
+
LATCH
EN
REF
BUFF
2.5V
REFERENCE
AD974
SWITCHED 16
CAP ADC
SERIAL
INTERFACE
CLOCK
EXT/INT
DATACLK
DATA
R/C
CS
SYNC
CONTROL LOGIC
&
CALIBRATION CIRCUITRY
AGND1 AGND2 A0 A1 WR1 WR2
BUSY DGND
PRODUCT HIGHLIGHTS
1. The AD974 is a complete data acquisition system combining
a four-channel multiplexer, a 16-bit sampling ADC and a
+2.5 V reference on a single chip.
2. The part operates from a single +5 V supply and also has a
power-down feature.
3. Interfacing to the AD974 is simple with a low number of
interconnect signals.
4. The AD974 is comprehensively specified for ac parameters
such as SNR and THD, as well as dc parameters such as
linearity and offset and gain errors.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999






AD974 Datasheet, Funktion
AD974
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY ERROR (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
FULL-SCALE ERROR
The last + transition (from 011 . . . 10 to 011 . . . 11) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale (9.9995422 V for a ±10 V range). The full-scale error is
the deviation of the actual level of the last transition from the
ideal level.
BIPOLAR ZERO ERROR
Bipolar zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the mid-
scale output code.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. Unipolar zero error is the devia-
tion of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGE
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of a full-scale input signal and is ex-
pressed in decibels.
SIGNAL TO (NOISE AND DISTORTION) (S/[N+D]) RATIO
S/(N+D) is the ratio of the rms value of the measured input
signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for S/(N+D) is expressed in decibels.
FULL POWER BANDWIDTH
The full power bandwidth is defined as the full-scale input fre-
quency at which the S/(N+D) degrades to 60 dB, 10 bits of
accuracy.
APERTURE DELAY
Aperture delay is a measure of the acquisition performance, and
is measured from the falling edge of the R/C input to when the
input signal is held for a conversion.
TRANSIENT RESPONSE
The time required for the AD974 to achieve its rated accuracy
after a full-scale step function is applied to its input.
OVERVOLTAGE RECOVERY
The time required for the ADC to recover to full accuracy after
an analog input signal 150% of full-scale is reduced to 50% of
the full-scale value.
–6– REV. A

6 Page









AD974 pdf, datenblatt
AD974
EXTERNAL CONTINUOUS CLOCK DATA READ DURING
CONVERSION WITH SYNC OUTPUT GENERATED
Figure 9 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a continu-
ous external clock with the generation of a SYNC output. What
permits the generation of a SYNC output is a transition of
DATACLK either while CS is high or while both CS and R/C
are low.
With a continuous clock the CS pin cannot be tied low as it
could be with a discontinuous clock. Use of a continuous clock
while a conversion is occurring can increase the DNL and
Transition Noise.
In Figure 9 a conversion is initiated by taking R/C low with CS
held low. While this condition exists a transition of DATACLK,
clock pulse #0, will enable the generation of a SYNC pulse. Less
then 83 ns after R/C is taken low the BUSY output will go low
to indicate that the conversion process has began. Figure 9
shows R/C then going high and after a delay of greater than
15 ns (t15), clock pulse #1 can be taken high to request the
SYNC output. The SYNC output will appear approximately
50 ns after this rising edge and will be valid on the falling edge
of clock pulse #1 and the rising edge of clock pulse #2. The
MSB will be valid approximately 40 ns after the rising edge of
clock pulse #2 and can be latched off either the falling edge of
clock pulse #2 or the rising edge of clock pulse #3. The LSB
will be valid on the falling edge of clock pulse #17 and the
rising edge of clock pulse #18.
Data should be clocked out during the 1st half of BUSY to
not degrade conversion performance. This requires use of a
10 MHz DATACLK or greater, with data being read out as
soon as the conversion process begins.
EXT
DATACLK
CS
t16
R/C
BUSY
SYNC
DATA
t12
t13
t14
0123
t15
t1
t2
t17
t12
t20
t18
BIT 15
(MSB)
18
t19
BIT 0
(LSB)
t18
Figure 9. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion
Using An External Continuous Data Clock (EXT/ INT Set to Logic High)
–12–
REV. A

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