AD9726 Datasheet PDF - Analog Devices
| Part Number | AD9726 | |
| Description | Digital-to-Analog Converter | |
| Manufacturers | Analog Devices | |
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FEATURES
Dynamic performance
SFDR ≥ 78 dBc at fOUT = 20 MHz
IMD ≥ 82 dBc at fOUT = 70 MHz
ACLR ≥ 76 dBc at fOUT = 70 MHz
NSD ≤ −160 dB/Hz at fOUT = 70 MHz
Precision calibrated linearity
DNL ≤ ±0.5 LSB at +25°C
INL ≤ ±1.0 LSB at +25°C
THD ≤ −95 dB at fOUT = 1 MHz
LVDS inputs with internal 100 Ω terminations
Automatic data/clock timing synchronization
Single data rate or double data rate capable
Differential current outputs
Internal precision reference
Operates on 2.5 V and 3.3 V supplies
Extended industrial temperature range
Thermally enhanced, 80-lead, RoHS-compliant
TQFP_EP package
APPLICATIONS
Instrumentation
Test equipment
Waveform synthesis
Communications systems
GENERAL DESCRIPTION
The AD9726 is a 16-bit digital-to-analog converter (DAC)
that offers leading edge performance at conversion rates of up
to 400 MSPS. The device uses low voltage differential signaling
(LVDS) inputs and includes internal 100 Ω terminations. The
analog output can be single-ended or differential current. An
internal precision reference is included.
The AD9726 also features synchronization logic to monitor and
optimize the timing between incoming data and the sample clock.
This reduces system complexity and simplifies timing require-
ments. An LVDS clock output is also available to drive an external
data pump in either single data rate (SDR) or double data rate
(DDR) mode.
All device operation is fully programmable using the flexible
serial port interface (SPI). The AD9726 is also fully functional
in its default state for applications without a controller.
16-Bit, 400 MSPS
Digital-to-Analog Converter
AD9726
FUNCTIONAL BLOCK DIAGRAM
CLK+
CLK–
DCLK_OUT+
DCLK_OUT–
CLOCK DISTRIBUTION
AND CONTROL
LVDS OUTPUT
DRIVER
SPI
CSB
SCLK
SDIO
SDO
RESET
DB[15]+
DB[15]–
DB[0]+
DB[0]–
DCLK_IN+
DCLK_IN–
CALIBRATION
MEMORY
16-BIT
DAC
INTERNAL
REFERENCE
Figure 1.
.
IOUTA
IOUTB
REFIO
FSADJ
PRODUCT HIGHLIGHTS
1. A unique combination of precision and performance
makes the AD9726 equally suited to applications with
demanding frequency domain or demanding time domain
requirements.
2. Nonvolatile factory calibration assures a highly linear
transfer function. Internal logic offers on demand self-
calibration for linearity even at extended operating
temperatures.
3. Proprietary architecture minimizes data dependent,
discrete mixing spurs and offers enhanced dynamic
performance over a wide range of output frequencies.
High input data rates create a very high frequency
synthesis bandwidth.
4. The fully automatic, transparent synchronizer maintains
optimized timing between clock and data in real time and
offers programmable control options for added flexibility.
5. Full-scale output current is external resistor programmable.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005-2010 Analog Devices, Inc. All rights reserved.
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AD9726
AC SPECIFICATIONS
DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, IOUT-FS = 20 mA, internal reference,
TMIN to TMAX, unless otherwise specified.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Output Settling Time (tST) to 0.1%
Output Rise Time (10% to 90%)
Output Fall Time (90% to 10%)
Output Noise (IOUTFS = 20 mA)
TOTAL HARMONIC DISTORTION (THD)
fDAC = 400 MHz, fOUT = 1 MHz, 0 dBFS
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 400 MHz, 0 dBFS
fOUT = 20 MHz
fOUT = 70 MHz
fOUT = 140 MHz
fDAC = 400 MHz, –3 dBFS
fOUT = 20 MHz
fOUT = 70 MHz
fOUT = 140 MHz
fDAC = 200 MHz, 0 dBFS
fOUT = 20 MHz
fOUT = 70 MHz
fDAC = 200 MHz, –3 dBFS
fOUT = 20 MHz
fOUT = 70 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 400 MHz, 0 dBFS
fOUT1 = 20 MHz, fOUT2 = 21 MHz
fOUT1 = 70 MHz, fOUT2 = 71 MHz
fOUT1 = 140 MHz, fOUT2 = 141 MHz
ADJACENT CHANNEL LEAKAGE RATIO (ACLR)
fDATA = 245.76 MSPS, fCARRIER = 70 MHz, One-Carrier WCDMA
fDATA = 245.76 MSPS, fCARRIER = 70 MHz, Two-Carrier WCDMA
fDATA = 245.76 MSPS, fCARRIER1 = 70 MHz, Four-Carrier WCDMA
fDATA = 245.76 MSPS, fCARRIER1 = 70 MHz, Eight-Carrier WCDMA
NOISE SPECTRAL DENSITY (NSD)
fDAC = 400 MHz, fOUT = 70 MHz, 0 dBFS
fDAC = 400 MHz, fOUT = 70 MHz, –3 dBFS
fDAC = 400 MHz, fOUT = 70 MHz, –6 dBFS
UPDATE RATE
Min Typ Max Unit
10.5 ns
500 ns
500 ns
45 pA/√Hz
−95 dB
78 dBc
68 dBc
62 dBc
80 dBc
70 dBc
62 dBc
84 dBc
62 dBc
82 dBc
68 dBc
86 dBc
82 dBc
74 dBc
76 dBc
70 dBc
66 dBc
62 dBc
−160
dBm/Hz
−163
dBm/Hz
−165
dBm/Hz
0 400 MSPS
Rev. B | Page 4 of 24
Preview 5 Page |
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| Information | Total 25 Pages | |
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| Download | [ AD9726.PDF Datasheet ] | |
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