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PDF AD9725 Data sheet ( Hoja de datos )
| Número de pieza | AD9725 | |
| Descripción | 14-Bit/ 600+ MSPS D/A Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
FEATURES
600+ MSPS DAC update rate
16/14/12/10-bit resolution family
LVDS interface with built-in 100-termination resistors
Single data rate and double data rate capability
Excellent dynamic performance
SFDR = 63 dBc at 140 MHz
IMD = 73 dBc at 140 MHz
Differential current outputs: 2 mA to 20 mA
–40°C to +85°C temperature range operation
On-chip 1.20 V reference
Package: 80-lead thermally-enhanced TQFP
Versatile clock and data interface
APPLICATIONS
Instrumentation and test
Wideband communications systems
Point-to-point wireless
LMDS
PA linearization
High resolution displays
PRODUCT DESCRIPTION
The AD9725 is a 14-bit digital-to-analog converter (DAC) that
utilizes an LVDS interface to achieve conversion rates in excess
of 600 MSPS. It is in a family of pin compatible converters that
offers selection of 10-bit, 12-bit, 14-bit, and 16-bit resolution
grades. All of the devices share the same interface options, small
outline package, and pinout, providing an upward or downward
component selection path based on performance, resolution
and cost.
14-Bit, 600+ MSPS
D/A Converter
AD9725
FUNCTIONAL BLOCK DIAGRAM
CALIBRATION
REFERENCE
FSADJ
REFIO
DB[13:0]+
DB[13:0]–
DATA
FORMATTER
DATA SYNC.
14-BIT
DAC
DDR
DATACLK_IN+
DATACLK_IN–
REXT
DATACLK_OUT+
DATACLK_OUT–
DATA CLOCK
FORMATTER
CLOCK DISTRIBUTION
AND CONTROL
SPI
CLK+
CLK–
Figure 1
IOUTA
IOUTB
SDIO
SDO/SYNC_ALRM
CSB
SCLK/SYNC_UPD
RESET
PRODUCT HIGHLIGHTS
Ultralow noise and intermodulation distortion (IMD) enable
high quality waveform synthesis at intermediate frequencies up
to 200 MHz.
LVDS receivers support SDR or DDR modes, with the maxi-
mum conversion rate exceeding 600 MSPS.
Manufactured on a CMOS process, the AD9725 uses a proprie-
tary switching technique that enhances dynamic performance.
The current output of the AD9725 can be easily configured for
various single-ended or differential circuit topologies.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
AD9725
DIGITAL SPECIFICATIONS
Table 3. TMIN to TMAX, AVDD1, AVDD2, DBVDD = 3.3 V, ADVDD, ACVDD, CLKVDD, DVDD = 2.5 V , IOUTFS = 20 mA, unless
otherwise noted. Specifications subject to change without notice.
Parameter
Conditions
Min Typ Max Unit
Digital Inputs
VCM = 0.875 V to 1.575 V
Differential Logic ‘1’
(put into footnote, and delete 0.1
column?)
0.6 V
Differential Logic ‘0’
–0.6 –0.1 V
Logic ‘1’ current
3.5 mA
Logic ‘0’ current
3.5 mA
Differential Input Resistance
100 W
Differential Input Capacitance
3 pF
Data Setup Time (tDS)
0.9 ns
Data Hold Time (tDH)
–0.3 ns
Data Clock Output Delay ( tDCO)
2.4 ns
Serial Control Bus
Maximum SCLK Frequency (fSCLK)
15 MHz
Minimum Clock Pulse Width High (tPWH)
30 ns
Minimum Clock Pulse Width Low (tPWL)
30 ns
Maximum Clock Rise/Fall Time
1 ms
Minimum Data/Chip Select Set Up Time (tDS)
25 ns
Minimum Data Hold Time (tDH)
0 ns
Maximum Data Valid Time (tDV)
30 ns
RESET Pulse Width
1.5 ns
Inputs (SDI, SDIO, SCLK, CSB)
Logic ‘1’ Voltage
2.1 3
V
Logic ‘0’ Voltage
0 0.9 V
Logic ‘1’ Current
–10 +10 µA
Logic ‘0’ Current
–10 +10 µA
Input Capacitance
5 pF
SDIO Output
Logic ‘1’ Voltage
DRVDD–0.6
V
Logic ‘0’ Voltage
0.4 V
Logic ‘1’ Current
30 50 mA
Logic ‘0’ Current
30 50 mA
DIGITAL TIMING INFORMATION
tDCO
CLK
DATACLK_OUT
DB[15:0]
DATACLK_IN
tDS
tDH
Figure 2. Single Datarate (SDR) Mode
CLK
DATACLK_OUT
DB[15:0]
DATACLK_IN
tDCO
tDS tDH tDS tDH
Figure 3. Double Datarate (DDR) Mode
Rev. PrA | Page 5 of 16
5 Page 
Preliminary Technical Data
DEFINITIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero-scale to full-scale.
Differential Nonlinearity ( DNL)
DNL is the measure of the variation in analog value, normalized
to full-scale, and associated with a 1 LSB change in digital input
code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree celsius. For reference drift, the drift is
reported in ppm per degree celsius.
AD9725
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in decibels, between the rms amplitude of the
output signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).
Signal-to-Noise Ratio (SNR)
S/N is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc. The
value for SNR is expressed in decibels.
Adjacent Channel Power Ratio (or ACPR)
A ratio in dBc between the measured power within a channel
relative to its adjacent channel.
LVDS
Low voltage differential signaling. A differential logic specifi-
cation that defines logic levels as approximately ±350 mV
(differential) over a common mode range of 0.875 V to 1.575 V.
LVDS is designed to achieve clock rates of up to 840 MHz.
Rev. PrA | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD9725.PDF ] | |
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