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PDF AD96687 Data sheet ( Hoja de datos )
| Número de pieza | AD96687 | |
| Descripción | Ultrafast Comparators | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Fast: 2.5 ns Propagation Delay
Low Power: 118 mW per Comparator
Packages: DIP, SOIC, PLCC
Power Supplies: +5 V, –5.2 V
Logic Compatibility: ECL
50 ps Delay Dispersion
APPLICATIONS
High Speed Triggers
High Speed Line Receivers
Threshold Detectors
Window Comparators
Peak Detectors
Ultrafast Comparators
AD96685/AD96687
AD96685 FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
INVERTING
INPUT
Q OUTPUT
Q OUTPUT
RL RL
LATCH
ENABLE
VT
AD96687 FUNCTIONAL BLOCK DIAGRAM
NONINVERTING
INPUT
Q OUTPUT Q OUTPUT
NONINVERTING
INPUT
Q OUTPUT Q OUTPUT
INVERTING
INPUT
RL RL
RL RL
INVERTING
INPUT
LE LE
LE LE
LATCH VT LATCH
ENABLE
ENABLE
THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL
PULL-DOWN RESISTORS.THESE RESISTORS MAY BE IN THE
RANGE OF 50⍀-200⍀ CONNECTED TO –2.0V, OR 200⍀-2000⍀
GENERAL DESCRIPTION
The AD96685 and AD96687 are ultrafast voltage comparators.
The AD96685 is a single comparator with 2.5 ns propagation
delay; the AD96687 is an equally fast dual comparator. Both
devices feature 50 ps propagation delay dispersion which is a
particularly important characteristic of high-speed comparators.
It is a measure of the difference in propagation delay under
differing overdrive conditions.
A fast, high precision differential input stage permits consistent
propagation delay with a wide variety of signals in the common-
mode range from –2.5 V to +5 V. Outputs are complementary
digital signals fully compatible with ECL 10 K and 10 KH logic
families. The outputs provide sufficient drive current to directly
drive transmission lines terminated in 50 Ω to –2 V. A level
sensitive latch input which permits tracking, track-hold, or
sample-hold modes of operation is included.
The AD96685 is available in industrial –25°C to +85°C range
in 16-pin SOIC.
The AD96687 is available in industrial range –25°C to +85°C,
in 16-pin DIP, SOIC, and 20-lead PLCC.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
Typical Performance Characteristics–AD96685/AD96687
APPLICATIONS INFORMATION
The AD96685/AD96687 comparators are very high speed devices.
Consequently, high speed design techniques must be employed
to achieve the best performance. The most critical aspect of any
AD96685/AD96687 design is the use of a low impedance
ground plane.
Another area of particular importance is power supply decoupling.
Normally, both power supply connections should be separately
decoupled to ground through 0.1 µF ceramic and 0.001 µF mica
capacitors. The basic design of comparator circuits makes the
negative supply somewhat more sensitive to variations. As a
result, more attention should be placed on ensuring a “clean”
negative supply.
The LATCH ENABLE input is active LOW (latched). If the
latching function is not used, the LATCH ENABLE input should
be grounded (ground is an ECL logic HIGH). The LATCH
ENABLE input of the AD96687 should be tied to –2.0 V or left
“floating,” to disable the latching function. An alternate use of
the LATCH ENABLE input is as a hysteresis control input. By
varying the voltage at the LATCH ENABLE input for the
AD96685 and the differential voltage between both latch
inputs for the AD96687, small variations in the hysteresis can
be achieved.
Occasionally, one of the two comparator stages within the
AD96687 will not be used. The inputs of the unused comparator
should not be allowed to “float.” The high internal gain may
cause the output to oscillate (possibly affecting the other com-
parator which is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two
inputs are at least one diode drop apart, while also grounding
the LATCH ENABLE input.
The best performance will be achieved with the use of proper
ECL terminations. The open-emitter outputs of the AD96685/
AD96687 are designed to be terminated through 50 Ω resis-
tors to –2.0 V, or any other equivalent ECL termination. If high
speed ECL signals must be routed more than a few centimeters,
MicroStrip or StripLine techniques may be required to ensure
proper transition times and prevent output ringing.
The AD96685/AD96687 have been specifically designed to
reduce propagation delay dispersion over an input overdrive
range of 100 mV to 1 V. Propagation delay dispersion is the
change in propagation delay which results from a change in
the degree of overdrive (how far the switching point is exceeded
by the input). The overall result is a higher degree of timing
accuracy since the AD96685/AD96687 are far less sensitive
to input variations than most comparator designs.
REV. D
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD96687.PDF ] | |
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